misc.isa (12541:de165cf2809e) misc.isa (12542:03cb745f9982)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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57 "thumb_semihost": '0xAB',
58 "arm_semihost": '0x123456' },
59 ["IsSyscall", "IsNonSpeculative",
60 "IsSerializeAfter"])
61 header_output = ImmOpDeclare.subst(svcIop)
62 decoder_output = SemihostConstructor.subst(svcIop)
63 exec_output = PredOpExecute.subst(svcIop)
64
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 48 unchanged lines hidden (view full) ---

57 "thumb_semihost": '0xAB',
58 "arm_semihost": '0x123456' },
59 ["IsSyscall", "IsNonSpeculative",
60 "IsSerializeAfter"])
61 header_output = ImmOpDeclare.subst(svcIop)
62 decoder_output = SemihostConstructor.subst(svcIop)
63 exec_output = PredOpExecute.subst(svcIop)
64
65 hltCode = '''
66 ThreadContext *tc = xc->tcBase();
67
68 const auto semihost_imm = Thumb? 0x3C : 0xF000;
69
70 if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
71 R0 = ArmSystem::callSemihosting32(tc, R0, R1);
72 } else {
73 // HLT instructions aren't implemented, so treat them as undefined
74 // instructions.
75 fault = std::make_shared<UndefinedInstruction>(
76 machInst, false, mnemonic);
77 }
78 '''
79
80 hltIop = InstObjParams("hlt", "Hlt", "ImmOp",
81 { "code": hltCode,
82 "predicate_test": predicateTest,
83 "thumb_semihost": '0x3C',
84 "arm_semihost": '0xF000' },
85 ["IsNonSpeculative"])
86 header_output += ImmOpDeclare.subst(hltIop)
87 decoder_output += SemihostConstructor.subst(hltIop)
88 exec_output += PredOpExecute.subst(hltIop)
89
65 smcCode = '''
66 HCR hcr = Hcr;
67 CPSR cpsr = Cpsr;
68 SCR scr = Scr;
69
70 if ((cpsr.mode != MODE_USER) && FullSystem) {
71 if (ArmSystem::haveVirtualization(xc->tcBase()) &&
72 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {

--- 1175 unchanged lines hidden --- 		90 smcCode = '''
91 HCR hcr = Hcr;
92 CPSR cpsr = Cpsr;
93 SCR scr = Scr;
94
95 if ((cpsr.mode != MODE_USER) && FullSystem) {
96 if (ArmSystem::haveVirtualization(xc->tcBase()) &&
97 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {

--- 1175 unchanged lines hidden ---