misc.isa (12261:88f4f45ec80c) misc.isa (12358:386d26feb00f)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1058 '''
1059 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
1060 { "code": clrexCode,
1061 "predicate_test": predicateTest },[])
1062 header_output += BasicDeclare.subst(clrexIop)
1063 decoder_output += BasicConstructor.subst(clrexIop)
1064 exec_output += PredOpExecute.subst(clrexIop)
1065
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 1049 unchanged lines hidden (view full) ---

1058 '''
1059 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
1060 { "code": clrexCode,
1061 "predicate_test": predicateTest },[])
1062 header_output += BasicDeclare.subst(clrexIop)
1063 decoder_output += BasicConstructor.subst(clrexIop)
1064 exec_output += PredOpExecute.subst(clrexIop)
1065
1066 McrDcCheckCode = '''
1067 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
1068 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
1069 RegId(MiscRegClass, preFlatDest)).index();
1070 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
1071 Hcptr, imm);
1072 bool can_write, undefined;
1073 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
1074
1075 // if we're in non secure PL1 mode then we can trap regardless
1076 // of whether the register is accessible, in other modes we
1077 // trap if only if the register IS accessible.
1078 if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
1079 !inSecureState(Scr, Cpsr)))) {
1080 return std::make_shared<UndefinedInstruction>(machInst, false,
1081 mnemonic);
1082 }
1083 if (hypTrap) {
1084 return std::make_shared<HypervisorTrap>(machInst, imm,
1085 EC_TRAPPED_CP15_MCR_MRC);
1086 }
1087 '''
1088
1089 McrDcimvacCode = '''
1090 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
1091 Request::INVALIDATE |
1092 Request::DST_POC);
1093 EA = Op1;
1094 '''
1095 McrDcimvacIop = InstObjParams("mcr dcimvac", "McrDcimvac",
1096 "MiscRegRegImmMemOp",
1097 {"memacc_code": McrDcCheckCode,
1098 "postacc_code": "",
1099 "ea_code": McrDcimvacCode,
1100 "predicate_test": predicateTest},
1101 ['IsMemRef', 'IsStore'])
1102 header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop)
1103 decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop)
1104 exec_output += Mcr15Execute.subst(McrDcimvacIop) + \
1105 Mcr15InitiateAcc.subst(McrDcimvacIop) + \
1106 Mcr15CompleteAcc.subst(McrDcimvacIop)
1107
1108 McrDccmvacCode = '''
1109 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
1110 Request::CLEAN |
1111 Request::DST_POC);
1112 EA = Op1;
1113 '''
1114 McrDccmvacIop = InstObjParams("mcr dccmvac", "McrDccmvac",
1115 "MiscRegRegImmMemOp",
1116 {"memacc_code": McrDcCheckCode,
1117 "postacc_code": "",
1118 "ea_code": McrDccmvacCode,
1119 "predicate_test": predicateTest},
1120 ['IsMemRef', 'IsStore'])
1121 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop)
1122 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop)
1123 exec_output += Mcr15Execute.subst(McrDccmvacIop) + \
1124 Mcr15InitiateAcc.subst(McrDccmvacIop) + \
1125 Mcr15CompleteAcc.subst(McrDccmvacIop)
1126
1127 McrDccmvauCode = '''
1128 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
1129 Request::CLEAN |
1130 Request::DST_POU);
1131 EA = Op1;
1132 '''
1133 McrDccmvauIop = InstObjParams("mcr dccmvau", "McrDccmvau",
1134 "MiscRegRegImmMemOp",
1135 {"memacc_code": McrDcCheckCode,
1136 "postacc_code": "",
1137 "ea_code": McrDccmvauCode,
1138 "predicate_test": predicateTest},
1139 ['IsMemRef', 'IsStore'])
1140 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop)
1141 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop)
1142 exec_output += Mcr15Execute.subst(McrDccmvauIop) + \
1143 Mcr15InitiateAcc.subst(McrDccmvauIop) + \
1144 Mcr15CompleteAcc.subst(McrDccmvauIop)
1145
1146 McrDccimvacCode = '''
1147 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
1148 Request::CLEAN |
1149 Request::INVALIDATE |
1150 Request::DST_POC);
1151 EA = Op1;
1152 '''
1153 McrDccimvacIop = InstObjParams("mcr dccimvac", "McrDccimvac",
1154 "MiscRegRegImmMemOp",
1155 {"memacc_code": McrDcCheckCode,
1156 "postacc_code": "",
1157 "ea_code": McrDccimvacCode,
1158 "predicate_test": predicateTest},
1159 ['IsMemRef', 'IsStore'])
1160 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
1161 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
1162 exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
1163 Mcr15InitiateAcc.subst(McrDccimvacIop) + \
1164 Mcr15CompleteAcc.subst(McrDccimvacIop)
1165
1066 isbCode = '''
1067 // If the barrier is due to a CP15 access check for hyp traps
1068 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
1069 Hdcr, Hstr, Hcptr, imm)) {
1070 return std::make_shared<HypervisorTrap>(machInst, imm,
1071 EC_TRAPPED_CP15_MCR_MRC);
1072 }
1073 '''

--- 82 unchanged lines hidden --- 		1166 isbCode = '''
1167 // If the barrier is due to a CP15 access check for hyp traps
1168 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
1169 Hdcr, Hstr, Hcptr, imm)) {
1170 return std::make_shared<HypervisorTrap>(machInst, imm,
1171 EC_TRAPPED_CP15_MCR_MRC);
1172 }
1173 '''

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