misc.isa (11939:9d1795bb5931) misc.isa (12106:7784fac1b159)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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808 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
809 { "code": bfiCode,
810 "predicate_test": predicateTest }, [])
811 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
812 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
813 exec_output += PredOpExecute.subst(bfiIop)
814
815 mrc14code = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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808 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
809 { "code": bfiCode,
810 "predicate_test": predicateTest }, [])
811 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
812 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
813 exec_output += PredOpExecute.subst(bfiIop)
814
815 mrc14code = '''
816 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1);
816 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
817 RegId(MiscRegClass, op1)).index();
817 bool can_read, undefined;
818 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
819 if (!can_read || undefined) {
820 return std::make_shared<UndefinedInstruction>(machInst, false,
821 mnemonic);
822 }
823 if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
824 Hstr, Hcptr, imm)) {

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832 { "code": mrc14code,
833 "predicate_test": predicateTest }, [])
834 header_output += RegRegImmOpDeclare.subst(mrc14Iop)
835 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
836 exec_output += PredOpExecute.subst(mrc14Iop)
837
838
839 mcr14code = '''
818 bool can_read, undefined;
819 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
820 if (!can_read || undefined) {
821 return std::make_shared<UndefinedInstruction>(machInst, false,
822 mnemonic);
823 }
824 if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
825 Hstr, Hcptr, imm)) {

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833 { "code": mrc14code,
834 "predicate_test": predicateTest }, [])
835 header_output += RegRegImmOpDeclare.subst(mrc14Iop)
836 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
837 exec_output += PredOpExecute.subst(mrc14Iop)
838
839
840 mcr14code = '''
840 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
841 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
842 RegId(MiscRegClass, dest)).index();
841 bool can_write, undefined;
842 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
843 if (undefined || !can_write) {
844 return std::make_shared<UndefinedInstruction>(machInst, false,
845 mnemonic);
846 }
847 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
848 Hstr, Hcptr, imm)) {

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857 ["IsSerializeAfter","IsNonSpeculative"])
858 header_output += RegRegImmOpDeclare.subst(mcr14Iop)
859 decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
860 exec_output += PredOpExecute.subst(mcr14Iop)
861
862 mrc15code = '''
863 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
864 MiscRegIndex miscReg = (MiscRegIndex)
843 bool can_write, undefined;
844 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
845 if (undefined || !can_write) {
846 return std::make_shared<UndefinedInstruction>(machInst, false,
847 mnemonic);
848 }
849 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
850 Hstr, Hcptr, imm)) {

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859 ["IsSerializeAfter","IsNonSpeculative"])
860 header_output += RegRegImmOpDeclare.subst(mcr14Iop)
861 decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
862 exec_output += PredOpExecute.subst(mcr14Iop)
863
864 mrc15code = '''
865 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
866 MiscRegIndex miscReg = (MiscRegIndex)
865 xc->tcBase()->flattenMiscIndex(preFlatOp1);
867 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
868 preFlatOp1)).index();
866 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
867 Hcptr, imm);
868 bool can_read, undefined;
869 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
870 // if we're in non secure PL1 mode then we can trap regargless of whether
871 // the register is accessable, in other modes we trap if only if the register
872 // IS accessable.
873 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&

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888 header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
889 decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
890 exec_output += PredOpExecute.subst(mrc15Iop)
891
892
893 mcr15code = '''
894 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
895 MiscRegIndex miscReg = (MiscRegIndex)
869 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
870 Hcptr, imm);
871 bool can_read, undefined;
872 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
873 // if we're in non secure PL1 mode then we can trap regargless of whether
874 // the register is accessable, in other modes we trap if only if the register
875 // IS accessable.
876 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&

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891 header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
892 decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
893 exec_output += PredOpExecute.subst(mrc15Iop)
894
895
896 mcr15code = '''
897 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
898 MiscRegIndex miscReg = (MiscRegIndex)
896 xc->tcBase()->flattenMiscIndex(preFlatDest);
899 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
900 preFlatDest)).index();
897 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
898 Hcptr, imm);
899 bool can_write, undefined;
900 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
901
902 // if we're in non secure PL1 mode then we can trap regargless of whether
903 // the register is accessable, in other modes we trap if only if the register
904 // IS accessable.

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920 header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
921 decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
922 exec_output += PredOpExecute.subst(mcr15Iop)
923
924
925 mrrc15code = '''
926 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
927 MiscRegIndex miscReg = (MiscRegIndex)
901 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
902 Hcptr, imm);
903 bool can_write, undefined;
904 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
905
906 // if we're in non secure PL1 mode then we can trap regargless of whether
907 // the register is accessable, in other modes we trap if only if the register
908 // IS accessable.

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924 header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
925 decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
926 exec_output += PredOpExecute.subst(mcr15Iop)
927
928
929 mrrc15code = '''
930 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
931 MiscRegIndex miscReg = (MiscRegIndex)
928 xc->tcBase()->flattenMiscIndex(preFlatOp1);
932 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
933 preFlatOp1)).index();
929 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
930 bool can_read, undefined;
931 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
932 // if we're in non secure PL1 mode then we can trap regargless of whether
933 // the register is accessable, in other modes we trap if only if the register
934 // IS accessable.
935 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
936 !inSecureState(Scr, Cpsr)))) {

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950 header_output += MrrcOpDeclare.subst(mrrc15Iop)
951 decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
952 exec_output += PredOpExecute.subst(mrrc15Iop)
953
954
955 mcrr15code = '''
956 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
957 MiscRegIndex miscReg = (MiscRegIndex)
934 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
935 bool can_read, undefined;
936 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
937 // if we're in non secure PL1 mode then we can trap regargless of whether
938 // the register is accessable, in other modes we trap if only if the register
939 // IS accessable.
940 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
941 !inSecureState(Scr, Cpsr)))) {

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955 header_output += MrrcOpDeclare.subst(mrrc15Iop)
956 decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
957 exec_output += PredOpExecute.subst(mrrc15Iop)
958
959
960 mcrr15code = '''
961 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
962 MiscRegIndex miscReg = (MiscRegIndex)
958 xc->tcBase()->flattenMiscIndex(preFlatDest);
963 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
964 preFlatDest)).index();
959 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
960 bool can_write, undefined;
961 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
962
963 // if we're in non secure PL1 mode then we can trap regargless of whether
964 // the register is accessable, in other modes we trap if only if the register
965 // IS accessable.
966 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&

--- 155 unchanged lines hidden --- 		965 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
966 bool can_write, undefined;
967 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
968
969 // if we're in non secure PL1 mode then we can trap regargless of whether
970 // the register is accessable, in other modes we trap if only if the register
971 // IS accessable.
972 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&

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