misc.isa (11355:46c7b3e35720) misc.isa (11939:9d1795bb5931)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
3// Copyright (c) 2010-2013,2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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809 { "code": bfiCode,
810 "predicate_test": predicateTest }, [])
811 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
812 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
813 exec_output += PredOpExecute.subst(bfiIop)
814
815 mrc14code = '''
816 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1);
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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809 { "code": bfiCode,
810 "predicate_test": predicateTest }, [])
811 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
812 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
813 exec_output += PredOpExecute.subst(bfiIop)
814
815 mrc14code = '''
816 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1);
817 if (!canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) {
817 bool can_read, undefined;
818 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
819 if (!can_read || undefined) {
818 return std::make_shared<UndefinedInstruction>(machInst, false,
819 mnemonic);
820 }
821 if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
822 Hstr, Hcptr, imm)) {
823 return std::make_shared<HypervisorTrap>(machInst, imm,
824 EC_TRAPPED_CP14_MCR_MRC);
825 }

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831 "predicate_test": predicateTest }, [])
832 header_output += RegRegImmOpDeclare.subst(mrc14Iop)
833 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
834 exec_output += PredOpExecute.subst(mrc14Iop)
835
836
837 mcr14code = '''
838 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
820 return std::make_shared<UndefinedInstruction>(machInst, false,
821 mnemonic);
822 }
823 if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
824 Hstr, Hcptr, imm)) {
825 return std::make_shared<HypervisorTrap>(machInst, imm,
826 EC_TRAPPED_CP14_MCR_MRC);
827 }

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833 "predicate_test": predicateTest }, [])
834 header_output += RegRegImmOpDeclare.subst(mrc14Iop)
835 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
836 exec_output += PredOpExecute.subst(mrc14Iop)
837
838
839 mcr14code = '''
840 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
839 if (!canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) {
841 bool can_write, undefined;
842 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
843 if (undefined || !can_write) {
840 return std::make_shared<UndefinedInstruction>(machInst, false,
841 mnemonic);
842 }
843 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
844 Hstr, Hcptr, imm)) {
845 return std::make_shared<HypervisorTrap>(machInst, imm,
846 EC_TRAPPED_CP14_MCR_MRC);
847 }

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856 exec_output += PredOpExecute.subst(mcr14Iop)
857
858 mrc15code = '''
859 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
860 MiscRegIndex miscReg = (MiscRegIndex)
861 xc->tcBase()->flattenMiscIndex(preFlatOp1);
862 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
863 Hcptr, imm);
844 return std::make_shared<UndefinedInstruction>(machInst, false,
845 mnemonic);
846 }
847 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
848 Hstr, Hcptr, imm)) {
849 return std::make_shared<HypervisorTrap>(machInst, imm,
850 EC_TRAPPED_CP14_MCR_MRC);
851 }

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860 exec_output += PredOpExecute.subst(mcr14Iop)
861
862 mrc15code = '''
863 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
864 MiscRegIndex miscReg = (MiscRegIndex)
865 xc->tcBase()->flattenMiscIndex(preFlatOp1);
866 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
867 Hcptr, imm);
864 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
865
868 bool can_read, undefined;
869 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
866 // if we're in non secure PL1 mode then we can trap regargless of whether
867 // the register is accessable, in other modes we trap if only if the register
868 // IS accessable.
870 // if we're in non secure PL1 mode then we can trap regargless of whether
871 // the register is accessable, in other modes we trap if only if the register
872 // IS accessable.
869 if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr, Cpsr))) {
873 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
874 !inSecureState(Scr, Cpsr)))) {
870 return std::make_shared<UndefinedInstruction>(machInst, false,
871 mnemonic);
872 }
873 if (hypTrap) {
874 return std::make_shared<HypervisorTrap>(machInst, imm,
875 EC_TRAPPED_CP15_MCR_MRC);
876 }
877 Dest = MiscNsBankedOp1;

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886
887
888 mcr15code = '''
889 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
890 MiscRegIndex miscReg = (MiscRegIndex)
891 xc->tcBase()->flattenMiscIndex(preFlatDest);
892 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
893 Hcptr, imm);
875 return std::make_shared<UndefinedInstruction>(machInst, false,
876 mnemonic);
877 }
878 if (hypTrap) {
879 return std::make_shared<HypervisorTrap>(machInst, imm,
880 EC_TRAPPED_CP15_MCR_MRC);
881 }
882 Dest = MiscNsBankedOp1;

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891
892
893 mcr15code = '''
894 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
895 MiscRegIndex miscReg = (MiscRegIndex)
896 xc->tcBase()->flattenMiscIndex(preFlatDest);
897 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
898 Hcptr, imm);
894 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
899 bool can_write, undefined;
900 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
895
896 // if we're in non secure PL1 mode then we can trap regargless of whether
897 // the register is accessable, in other modes we trap if only if the register
898 // IS accessable.
901
902 // if we're in non secure PL1 mode then we can trap regargless of whether
903 // the register is accessable, in other modes we trap if only if the register
904 // IS accessable.
899 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
905 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
906 !inSecureState(Scr, Cpsr)))) {
900 return std::make_shared<UndefinedInstruction>(machInst, false,
901 mnemonic);
902 }
903 if (hypTrap) {
904 return std::make_shared<HypervisorTrap>(machInst, imm,
905 EC_TRAPPED_CP15_MCR_MRC);
906 }
907 MiscNsBankedDest = Op1;

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915 exec_output += PredOpExecute.subst(mcr15Iop)
916
917
918 mrrc15code = '''
919 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
920 MiscRegIndex miscReg = (MiscRegIndex)
921 xc->tcBase()->flattenMiscIndex(preFlatOp1);
922 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
907 return std::make_shared<UndefinedInstruction>(machInst, false,
908 mnemonic);
909 }
910 if (hypTrap) {
911 return std::make_shared<HypervisorTrap>(machInst, imm,
912 EC_TRAPPED_CP15_MCR_MRC);
913 }
914 MiscNsBankedDest = Op1;

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922 exec_output += PredOpExecute.subst(mcr15Iop)
923
924
925 mrrc15code = '''
926 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
927 MiscRegIndex miscReg = (MiscRegIndex)
928 xc->tcBase()->flattenMiscIndex(preFlatOp1);
929 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
923 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
924
930 bool can_read, undefined;
931 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
925 // if we're in non secure PL1 mode then we can trap regargless of whether
926 // the register is accessable, in other modes we trap if only if the register
927 // IS accessable.
932 // if we're in non secure PL1 mode then we can trap regargless of whether
933 // the register is accessable, in other modes we trap if only if the register
934 // IS accessable.
928 if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr, Cpsr))) {
935 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
936 !inSecureState(Scr, Cpsr)))) {
929 return std::make_shared<UndefinedInstruction>(machInst, false,
930 mnemonic);
931 }
932 if (hypTrap) {
933 return std::make_shared<HypervisorTrap>(machInst, imm,
934 EC_TRAPPED_CP15_MCRR_MRRC);
935 }
936 Dest = bits(MiscNsBankedOp164, 63, 32);

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944 exec_output += PredOpExecute.subst(mrrc15Iop)
945
946
947 mcrr15code = '''
948 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
949 MiscRegIndex miscReg = (MiscRegIndex)
950 xc->tcBase()->flattenMiscIndex(preFlatDest);
951 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
937 return std::make_shared<UndefinedInstruction>(machInst, false,
938 mnemonic);
939 }
940 if (hypTrap) {
941 return std::make_shared<HypervisorTrap>(machInst, imm,
942 EC_TRAPPED_CP15_MCRR_MRRC);
943 }
944 Dest = bits(MiscNsBankedOp164, 63, 32);

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952 exec_output += PredOpExecute.subst(mrrc15Iop)
953
954
955 mcrr15code = '''
956 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
957 MiscRegIndex miscReg = (MiscRegIndex)
958 xc->tcBase()->flattenMiscIndex(preFlatDest);
959 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
952 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
960 bool can_write, undefined;
961 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
953
954 // if we're in non secure PL1 mode then we can trap regargless of whether
955 // the register is accessable, in other modes we trap if only if the register
956 // IS accessable.
962
963 // if we're in non secure PL1 mode then we can trap regargless of whether
964 // the register is accessable, in other modes we trap if only if the register
965 // IS accessable.
957 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
966 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
967 !inSecureState(Scr, Cpsr)))) {
958 return std::make_shared<UndefinedInstruction>(machInst, false,
959 mnemonic);
960 }
961 if (hypTrap) {
962 return std::make_shared<HypervisorTrap>(machInst, imm,
963 EC_TRAPPED_CP15_MCRR_MRRC);
964 }
965 MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;

--- 146 unchanged lines hidden --- 		968 return std::make_shared<UndefinedInstruction>(machInst, false,
969 mnemonic);
970 }
971 if (hypTrap) {
972 return std::make_shared<HypervisorTrap>(machInst, imm,
973 EC_TRAPPED_CP15_MCRR_MRRC);
974 }
975 MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;

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