misc.isa (10501:e278fa3086b5) misc.isa (11150:a8a64cca231b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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644 SCR scr = Scr64;
645 SCTLR sctlr = Sctlr;
646
647 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
648 ThreadContext *tc = xc->tcBase();
649 if (SevMailbox == 1) {
650 SevMailbox = 0;
651 PseudoInst::quiesceSkip(tc);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 635 unchanged lines hidden (view full) ---

644 SCR scr = Scr64;
645 SCTLR sctlr = Sctlr;
646
647 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
648 ThreadContext *tc = xc->tcBase();
649 if (SevMailbox == 1) {
650 SevMailbox = 0;
651 PseudoInst::quiesceSkip(tc);
652 } else if (tc->getCpuPtr()->getInterruptController()->checkInterrupts(tc)) {
652 } else if (tc->getCpuPtr()->getInterruptController(
653 tc->threadId())->checkInterrupts(tc)) {
653 PseudoInst::quiesceSkip(tc);
654 } else if (cpsr.el == EL0 && !sctlr.ntwe) {
655 PseudoInst::quiesceSkip(tc);
656 fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00001,
657 EC_TRAPPED_WFI_WFE);
658 } else if (ArmSystem::haveVirtualization(tc) &&
659 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) &&
660 hcr.twe) {

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687 wfiCode = '''
688 HCR hcr = Hcr;
689 CPSR cpsr = Cpsr;
690 SCR scr = Scr64;
691 SCTLR sctlr = Sctlr;
692
693 // WFI doesn't sleep if interrupts are pending (masked or not)
694 ThreadContext *tc = xc->tcBase();
654 PseudoInst::quiesceSkip(tc);
655 } else if (cpsr.el == EL0 && !sctlr.ntwe) {
656 PseudoInst::quiesceSkip(tc);
657 fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00001,
658 EC_TRAPPED_WFI_WFE);
659 } else if (ArmSystem::haveVirtualization(tc) &&
660 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) &&
661 hcr.twe) {

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688 wfiCode = '''
689 HCR hcr = Hcr;
690 CPSR cpsr = Cpsr;
691 SCR scr = Scr64;
692 SCTLR sctlr = Sctlr;
693
694 // WFI doesn't sleep if interrupts are pending (masked or not)
695 ThreadContext *tc = xc->tcBase();
695 if (tc->getCpuPtr()->getInterruptController()->checkWfiWake(hcr, cpsr,
696 scr)) {
696 if (tc->getCpuPtr()->getInterruptController(
697 tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
697 PseudoInst::quiesceSkip(tc);
698 } else if (cpsr.el == EL0 && !sctlr.ntwi) {
699 PseudoInst::quiesceSkip(tc);
700 fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
701 EC_TRAPPED_WFI_WFE);
702 } else if (ArmSystem::haveVirtualization(tc) && hcr.twi &&
703 (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) {
704 PseudoInst::quiesceSkip(tc);
705 fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00000,
706 EC_TRAPPED_WFI_WFE);
707 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) {
708 PseudoInst::quiesceSkip(tc);
709 fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000,
710 EC_TRAPPED_WFI_WFE);
711 } else {
712 PseudoInst::quiesce(tc);
713 }
698 PseudoInst::quiesceSkip(tc);
699 } else if (cpsr.el == EL0 && !sctlr.ntwi) {
700 PseudoInst::quiesceSkip(tc);
701 fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
702 EC_TRAPPED_WFI_WFE);
703 } else if (ArmSystem::haveVirtualization(tc) && hcr.twi &&
704 (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) {
705 PseudoInst::quiesceSkip(tc);
706 fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00000,
707 EC_TRAPPED_WFI_WFE);
708 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) {
709 PseudoInst::quiesceSkip(tc);
710 fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000,
711 EC_TRAPPED_WFI_WFE);
712 } else {
713 PseudoInst::quiesce(tc);
714 }
714 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
715 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
715 '''
716 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
717 { "code" : wfiCode, "predicate_test" : predicateTest },
718 ["IsNonSpeculative", "IsQuiesce",
719 "IsSerializeAfter", "IsUnverifiable"])
720 header_output += BasicDeclare.subst(wfiIop)
721 decoder_output += BasicConstructor.subst(wfiIop)
722 exec_output += QuiescePredOpExecute.subst(wfiIop)
723
724 sevCode = '''
725 SevMailbox = 1;
726 System *sys = xc->tcBase()->getSystemPtr();
727 for (int x = 0; x < sys->numContexts(); x++) {
728 ThreadContext *oc = sys->getThreadContext(x);
729 if (oc == xc->tcBase())
730 continue;
731 // Wake CPU with interrupt if they were sleeping
732 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
733 // Post Interrupt and wake cpu if needed
716 '''
717 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
718 { "code" : wfiCode, "predicate_test" : predicateTest },
719 ["IsNonSpeculative", "IsQuiesce",
720 "IsSerializeAfter", "IsUnverifiable"])
721 header_output += BasicDeclare.subst(wfiIop)
722 decoder_output += BasicConstructor.subst(wfiIop)
723 exec_output += QuiescePredOpExecute.subst(wfiIop)
724
725 sevCode = '''
726 SevMailbox = 1;
727 System *sys = xc->tcBase()->getSystemPtr();
728 for (int x = 0; x < sys->numContexts(); x++) {
729 ThreadContext *oc = sys->getThreadContext(x);
730 if (oc == xc->tcBase())
731 continue;
732 // Wake CPU with interrupt if they were sleeping
733 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
734 // Post Interrupt and wake cpu if needed
734 oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
735 oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
735 }
736 }
737 '''
738 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
739 { "code" : sevCode, "predicate_test" : predicateTest },
740 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
741 header_output += BasicDeclare.subst(sevIop)
742 decoder_output += BasicConstructor.subst(sevIop)

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736 }
737 }
738 '''
739 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
740 { "code" : sevCode, "predicate_test" : predicateTest },
741 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
742 header_output += BasicDeclare.subst(sevIop)
743 decoder_output += BasicConstructor.subst(sevIop)

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