misc.isa (10037:5cac77888310) misc.isa (10188:c09802451018)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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846 xc->tcBase()->flattenMiscIndex(preFlatOp1);
847 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
848 Hcptr, imm);
849 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
850
851 // if we're in non secure PL1 mode then we can trap regargless of whether
852 // the register is accessable, in other modes we trap if only if the register
853 // IS accessable.
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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846 xc->tcBase()->flattenMiscIndex(preFlatOp1);
847 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
848 Hcptr, imm);
849 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
850
851 // if we're in non secure PL1 mode then we can trap regargless of whether
852 // the register is accessable, in other modes we trap if only if the register
853 // IS accessable.
854 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
854 if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr, Cpsr))) {
855 return new UndefinedInstruction(machInst, false, mnemonic);
856 }
857 if (hypTrap) {
858 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC);
859 }
860 Dest = MiscNsBankedOp1;
861 '''
862

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901 MiscRegIndex miscReg = (MiscRegIndex)
902 xc->tcBase()->flattenMiscIndex(preFlatOp1);
903 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
904 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
905
906 // if we're in non secure PL1 mode then we can trap regargless of whether
907 // the register is accessable, in other modes we trap if only if the register
908 // IS accessable.
855 return new UndefinedInstruction(machInst, false, mnemonic);
856 }
857 if (hypTrap) {
858 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC);
859 }
860 Dest = MiscNsBankedOp1;
861 '''
862

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901 MiscRegIndex miscReg = (MiscRegIndex)
902 xc->tcBase()->flattenMiscIndex(preFlatOp1);
903 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
904 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
905
906 // if we're in non secure PL1 mode then we can trap regargless of whether
907 // the register is accessable, in other modes we trap if only if the register
908 // IS accessable.
909 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
909 if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr, Cpsr))) {
910 return new UndefinedInstruction(machInst, false, mnemonic);
911 }
912 if (hypTrap) {
913 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC);
914 }
915 Dest = bits(MiscNsBankedOp164, 63, 32);
916 Dest2 = bits(MiscNsBankedOp164, 31, 0);
917 '''

--- 171 unchanged lines hidden --- 		910 return new UndefinedInstruction(machInst, false, mnemonic);
911 }
912 if (hypTrap) {
913 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC);
914 }
915 Dest = bits(MiscNsBankedOp164, 63, 32);
916 Dest2 = bits(MiscNsBankedOp164, 31, 0);
917 '''

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