1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010-2013 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 23 unchanged lines hidden (view full) --- 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 svcCode = ''' |
43 fault = new SupervisorCall(machInst, imm); |
44 ''' 45 |
46 svcIop = InstObjParams("svc", "Svc", "ImmOp", |
47 { "code": svcCode, 48 "predicate_test": predicateTest }, 49 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"]) |
50 header_output = ImmOpDeclare.subst(svcIop) 51 decoder_output = ImmOpConstructor.subst(svcIop) |
52 exec_output = PredOpExecute.subst(svcIop) 53 |
54 smcCode = ''' 55 HCR hcr = Hcr; 56 CPSR cpsr = Cpsr; 57 SCR scr = Scr; 58 59 if ((cpsr.mode != MODE_USER) && FullSystem) { 60 if (ArmSystem::haveVirtualization(xc->tcBase()) && 61 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) { 62 fault = new HypervisorTrap(machInst, 0, EC_SMC_TO_HYP); 63 } else { 64 if (scr.scd) { 65 fault = disabledFault(); 66 } else { 67 fault = new SecureMonitorCall(machInst); 68 } 69 } 70 } else { 71 fault = disabledFault(); 72 } 73 ''' 74 75 smcIop = InstObjParams("smc", "Smc", "PredOp", 76 { "code": smcCode, 77 "predicate_test": predicateTest }, 78 ["IsNonSpeculative", "IsSerializeAfter"]) 79 header_output += BasicDeclare.subst(smcIop) 80 decoder_output += BasicConstructor.subst(smcIop) 81 exec_output += PredOpExecute.subst(smcIop) 82 83 hvcCode = ''' 84 CPSR cpsr = Cpsr; 85 SCR scr = Scr; 86 87 // Filter out the various cases where this instruction isn't defined 88 if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) || 89 (cpsr.mode == MODE_USER) || 90 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { 91 fault = disabledFault(); 92 } else { 93 fault = new HypervisorCall(machInst, imm); 94 } 95 ''' 96 97 hvcIop = InstObjParams("hvc", "Hvc", "ImmOp", 98 { "code": hvcCode, 99 "predicate_test": predicateTest }, 100 ["IsNonSpeculative", "IsSerializeAfter"]) 101 header_output += ImmOpDeclare.subst(hvcIop) 102 decoder_output += ImmOpConstructor.subst(hvcIop) 103 exec_output += PredOpExecute.subst(hvcIop) 104 105 eretCode = ''' 106 SCTLR sctlr = Sctlr; 107 CPSR old_cpsr = Cpsr; 108 old_cpsr.nz = CondCodesNZ; 109 old_cpsr.c = CondCodesC; 110 old_cpsr.v = CondCodesV; 111 old_cpsr.ge = CondCodesGE; 112 113 CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, 114 true, sctlr.nmfi, xc->tcBase()); 115 Cpsr = ~CondCodesMask & new_cpsr; 116 CondCodesNZ = new_cpsr.nz; 117 CondCodesC = new_cpsr.c; 118 CondCodesV = new_cpsr.v; 119 CondCodesGE = new_cpsr.ge; 120 121 NextThumb = (new_cpsr).t; 122 NextJazelle = (new_cpsr).j; 123 NextItState = (((new_cpsr).it2 << 2) & 0xFC) 124 | ((new_cpsr).it1 & 0x3); 125 126 NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR; 127 ''' 128 129 eretIop = InstObjParams("eret", "Eret", "PredOp", 130 { "code": eretCode, 131 "predicate_test": predicateTest }, 132 ["IsNonSpeculative", "IsSerializeAfter"]) 133 header_output += BasicDeclare.subst(eretIop) 134 decoder_output += BasicConstructor.subst(eretIop) 135 exec_output += PredOpExecute.subst(eretIop) 136 137 138 |
139}}; 140 141let {{ 142 143 header_output = decoder_output = exec_output = "" 144 145 mrsCpsrCode = ''' 146 CPSR cpsr = Cpsr; --- 16 unchanged lines hidden (view full) --- 163 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 164 { "code": mrsSpsrCode, 165 "predicate_test": predicateTest }, 166 ["IsSerializeBefore"]) 167 header_output += MrsDeclare.subst(mrsSpsrIop) 168 decoder_output += MrsConstructor.subst(mrsSpsrIop) 169 exec_output += PredOpExecute.subst(mrsSpsrIop) 170 |
171 mrsBankedRegCode = ''' 172 bool isIntReg; 173 int regIdx; 174 175 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 176 if (isIntReg) { 177 Dest = DecodedBankedIntReg; 178 } else { 179 Dest = xc->readMiscReg(regIdx); 180 } 181 } else { 182 return new UndefinedInstruction(machInst, false, mnemonic); 183 } 184 ''' 185 mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp", 186 { "code": mrsBankedRegCode, 187 "predicate_test": predicateTest }, 188 ["IsSerializeBefore"]) 189 header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop) 190 decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop) 191 exec_output += PredOpExecute.subst(mrsBankedRegIop) 192 193 msrBankedRegCode = ''' 194 bool isIntReg; 195 int regIdx; 196 197 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 198 if (isIntReg) { 199 // This is a bit nasty, you would have thought that 200 // DecodedBankedIntReg wouldn't be written to unless the 201 // conditions on the IF statements above are met, however if 202 // you look at the generated C code you'll find that they are. 203 // However this is safe as DecodedBankedIntReg (which is used 204 // in operands.isa to get the index of DecodedBankedIntReg) 205 // will return INTREG_DUMMY if its not a valid integer 206 // register, so redirecting the write to somewhere we don't 207 // care about. 208 DecodedBankedIntReg = Op1; 209 } else { 210 xc->setMiscReg(regIdx, Op1); 211 } 212 } else { 213 return new UndefinedInstruction(machInst, false, mnemonic); 214 } 215 ''' 216 msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", 217 { "code": msrBankedRegCode, 218 "predicate_test": predicateTest }, 219 ["IsSerializeAfter"]) 220 header_output += MsrBankedRegDeclare.subst(msrBankedRegIop) 221 decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop) 222 exec_output += PredOpExecute.subst(msrBankedRegIop) 223 |
224 msrCpsrRegCode = ''' 225 SCTLR sctlr = Sctlr; 226 CPSR old_cpsr = Cpsr; 227 old_cpsr.nz = CondCodesNZ; 228 old_cpsr.c = CondCodesC; 229 old_cpsr.v = CondCodesV; 230 old_cpsr.ge = CondCodesGE; 231 232 CPSR new_cpsr = |
233 cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false, 234 sctlr.nmfi, xc->tcBase()); |
235 Cpsr = ~CondCodesMask & new_cpsr; 236 CondCodesNZ = new_cpsr.nz; 237 CondCodesC = new_cpsr.c; 238 CondCodesV = new_cpsr.v; 239 CondCodesGE = new_cpsr.ge; 240 ''' 241 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 242 { "code": msrCpsrRegCode, --- 15 unchanged lines hidden (view full) --- 258 msrCpsrImmCode = ''' 259 SCTLR sctlr = Sctlr; 260 CPSR old_cpsr = Cpsr; 261 old_cpsr.nz = CondCodesNZ; 262 old_cpsr.c = CondCodesC; 263 old_cpsr.v = CondCodesV; 264 old_cpsr.ge = CondCodesGE; 265 CPSR new_cpsr = |
266 cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false, 267 sctlr.nmfi, xc->tcBase()); |
268 Cpsr = ~CondCodesMask & new_cpsr; 269 CondCodesNZ = new_cpsr.nz; 270 CondCodesC = new_cpsr.c; 271 CondCodesV = new_cpsr.v; 272 CondCodesGE = new_cpsr.ge; 273 ''' 274 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 275 { "code": msrCpsrImmCode, --- 343 unchanged lines hidden (view full) --- 619 exec_output += PredOpExecute.subst(usada8Iop) 620 621 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 622 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 623 header_output += BasicDeclare.subst(bkptIop) 624 decoder_output += BasicConstructor.subst(bkptIop) 625 exec_output += BasicExecute.subst(bkptIop) 626 |
627 nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop']) |
628 header_output += BasicDeclare.subst(nopIop) |
629 decoder_output += BasicConstructor64.subst(nopIop) 630 exec_output += BasicExecute.subst(nopIop) |
631 632 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 633 { "code" : "", "predicate_test" : predicateTest }) 634 header_output += BasicDeclare.subst(yieldIop) 635 decoder_output += BasicConstructor.subst(yieldIop) 636 exec_output += PredOpExecute.subst(yieldIop) 637 638 wfeCode = ''' |
639 HCR hcr = Hcr; 640 CPSR cpsr = Cpsr; 641 SCR scr = Scr64; 642 SCTLR sctlr = Sctlr; 643 644 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending, 645 ThreadContext *tc = xc->tcBase(); |
646 if (SevMailbox == 1) { 647 SevMailbox = 0; |
648 PseudoInst::quiesceSkip(tc); 649 } else if (tc->getCpuPtr()->getInterruptController()->checkInterrupts(tc)) { 650 PseudoInst::quiesceSkip(tc); 651 } else if (cpsr.el == EL0 && !sctlr.ntwe) { 652 PseudoInst::quiesceSkip(tc); 653 fault = new SupervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE); 654 } else if (ArmSystem::haveVirtualization(tc) && 655 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && 656 hcr.twe) { 657 PseudoInst::quiesceSkip(tc); 658 fault = new HypervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE); 659 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twe) { 660 PseudoInst::quiesceSkip(tc); 661 fault = new SecureMonitorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE); |
662 } else { |
663 PseudoInst::quiesce(tc); |
664 } 665 ''' 666 wfePredFixUpCode = ''' 667 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps 668 // and SEV interrupts 669 SevMailbox = 1; 670 ''' 671 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 672 { "code" : wfeCode, 673 "pred_fixup" : wfePredFixUpCode, 674 "predicate_test" : predicateTest }, 675 ["IsNonSpeculative", "IsQuiesce", 676 "IsSerializeAfter", "IsUnverifiable"]) 677 header_output += BasicDeclare.subst(wfeIop) 678 decoder_output += BasicConstructor.subst(wfeIop) 679 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) 680 681 wfiCode = ''' |
682 HCR hcr = Hcr; 683 CPSR cpsr = Cpsr; 684 SCR scr = Scr64; 685 SCTLR sctlr = Sctlr; 686 |
687 // WFI doesn't sleep if interrupts are pending (masked or not) |
688 ThreadContext *tc = xc->tcBase(); 689 if (tc->getCpuPtr()->getInterruptController()->checkWfiWake(hcr, cpsr, 690 scr)) { 691 PseudoInst::quiesceSkip(tc); 692 } else if (cpsr.el == EL0 && !sctlr.ntwi) { 693 PseudoInst::quiesceSkip(tc); 694 fault = new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE); 695 } else if (ArmSystem::haveVirtualization(tc) && hcr.twi && 696 (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) { 697 PseudoInst::quiesceSkip(tc); 698 fault = new HypervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE); 699 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) { 700 PseudoInst::quiesceSkip(tc); 701 fault = new SecureMonitorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE); |
702 } else { |
703 PseudoInst::quiesce(tc); |
704 } |
705 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0); |
706 ''' 707 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 708 { "code" : wfiCode, "predicate_test" : predicateTest }, 709 ["IsNonSpeculative", "IsQuiesce", 710 "IsSerializeAfter", "IsUnverifiable"]) 711 header_output += BasicDeclare.subst(wfiIop) 712 decoder_output += BasicConstructor.subst(wfiIop) 713 exec_output += QuiescePredOpExecute.subst(wfiIop) --- 14 unchanged lines hidden (view full) --- 728 ''' 729 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 730 { "code" : sevCode, "predicate_test" : predicateTest }, 731 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 732 header_output += BasicDeclare.subst(sevIop) 733 decoder_output += BasicConstructor.subst(sevIop) 734 exec_output += PredOpExecute.subst(sevIop) 735 |
736 sevlCode = ''' 737 SevMailbox = 1; 738 ''' 739 sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \ 740 { "code" : sevlCode, "predicate_test" : predicateTest }, 741 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 742 header_output += BasicDeclare.subst(sevlIop) 743 decoder_output += BasicConstructor.subst(sevlIop) 744 exec_output += BasicExecute.subst(sevlIop) 745 |
746 itIop = InstObjParams("it", "ItInst", "PredOp", \ 747 { "code" : ";", 748 "predicate_test" : predicateTest }, []) 749 header_output += BasicDeclare.subst(itIop) 750 decoder_output += BasicConstructor.subst(itIop) 751 exec_output += PredOpExecute.subst(itIop) 752 unknownCode = ''' |
753 return new UndefinedInstruction(machInst, true); |
754 ''' 755 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 756 { "code": unknownCode, 757 "predicate_test": predicateTest }) 758 header_output += BasicDeclare.subst(unknownIop) 759 decoder_output += BasicConstructor.subst(unknownIop) 760 exec_output += PredOpExecute.subst(unknownIop) 761 --- 35 unchanged lines hidden (view full) --- 797 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 798 { "code": bfiCode, 799 "predicate_test": predicateTest }, []) 800 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 801 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 802 exec_output += PredOpExecute.subst(bfiIop) 803 804 mrc14code = ''' |
805 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1); 806 if (!canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) { 807 return new UndefinedInstruction(machInst, false, mnemonic); |
808 } |
809 if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr, 810 Hstr, Hcptr, imm)) { 811 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC); 812 } |
813 Dest = MiscOp1; 814 ''' 815 |
816 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp", |
817 { "code": mrc14code, 818 "predicate_test": predicateTest }, []) |
819 header_output += RegRegImmOpDeclare.subst(mrc14Iop) 820 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop) |
821 exec_output += PredOpExecute.subst(mrc14Iop) 822 823 824 mcr14code = ''' |
825 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest); 826 if (!canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) { 827 return new UndefinedInstruction(machInst, false, mnemonic); |
828 } |
829 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, 830 Hstr, Hcptr, imm)) { 831 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC); 832 } |
833 MiscDest = Op1; 834 ''' |
835 mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp", |
836 { "code": mcr14code, 837 "predicate_test": predicateTest }, 838 ["IsSerializeAfter","IsNonSpeculative"]) |
839 header_output += RegRegImmOpDeclare.subst(mcr14Iop) 840 decoder_output += RegRegImmOpConstructor.subst(mcr14Iop) |
841 exec_output += PredOpExecute.subst(mcr14Iop) 842 |
843 mrc15code = ''' |
844 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase()); 845 MiscRegIndex miscReg = (MiscRegIndex) 846 xc->tcBase()->flattenMiscIndex(preFlatOp1); 847 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 848 Hcptr, imm); 849 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase()); 850 851 // if we're in non secure PL1 mode then we can trap regargless of whether 852 // the register is accessable, in other modes we trap if only if the register 853 // IS accessable. 854 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) { 855 return new UndefinedInstruction(machInst, false, mnemonic); |
856 } |
857 if (hypTrap) { 858 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); 859 } 860 Dest = MiscNsBankedOp1; |
861 ''' 862 |
863 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegImmOp", |
864 { "code": mrc15code, 865 "predicate_test": predicateTest }, []) |
866 header_output += RegRegImmOpDeclare.subst(mrc15Iop) 867 decoder_output += RegRegImmOpConstructor.subst(mrc15Iop) |
868 exec_output += PredOpExecute.subst(mrc15Iop) 869 870 871 mcr15code = ''' |
872 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase()); 873 MiscRegIndex miscReg = (MiscRegIndex) 874 xc->tcBase()->flattenMiscIndex(preFlatDest); 875 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 876 Hcptr, imm); 877 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase()); 878 879 // if we're in non secure PL1 mode then we can trap regargless of whether 880 // the register is accessable, in other modes we trap if only if the register 881 // IS accessable. 882 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) { 883 return new UndefinedInstruction(machInst, false, mnemonic); |
884 } |
885 if (hypTrap) { 886 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); 887 } 888 MiscNsBankedDest = Op1; |
889 ''' |
890 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegImmOp", |
891 { "code": mcr15code, 892 "predicate_test": predicateTest }, 893 ["IsSerializeAfter","IsNonSpeculative"]) |
894 header_output += RegRegImmOpDeclare.subst(mcr15Iop) 895 decoder_output += RegRegImmOpConstructor.subst(mcr15Iop) |
896 exec_output += PredOpExecute.subst(mcr15Iop) 897 |
898 |
899 mrrc15code = ''' 900 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase()); 901 MiscRegIndex miscReg = (MiscRegIndex) 902 xc->tcBase()->flattenMiscIndex(preFlatOp1); 903 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 904 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase()); |
905 |
906 // if we're in non secure PL1 mode then we can trap regargless of whether 907 // the register is accessable, in other modes we trap if only if the register 908 // IS accessable. 909 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) { 910 return new UndefinedInstruction(machInst, false, mnemonic); 911 } 912 if (hypTrap) { 913 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC); 914 } 915 Dest = bits(MiscNsBankedOp164, 63, 32); 916 Dest2 = bits(MiscNsBankedOp164, 31, 0); 917 ''' 918 mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp", 919 { "code": mrrc15code, 920 "predicate_test": predicateTest }, []) 921 header_output += MrrcOpDeclare.subst(mrrc15Iop) 922 decoder_output += MrrcOpConstructor.subst(mrrc15Iop) 923 exec_output += PredOpExecute.subst(mrrc15Iop) 924 925 926 mcrr15code = ''' 927 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase()); 928 MiscRegIndex miscReg = (MiscRegIndex) 929 xc->tcBase()->flattenMiscIndex(preFlatDest); 930 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 931 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase()); 932 933 // if we're in non secure PL1 mode then we can trap regargless of whether 934 // the register is accessable, in other modes we trap if only if the register 935 // IS accessable. 936 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) { 937 return new UndefinedInstruction(machInst, false, mnemonic); 938 } 939 if (hypTrap) { 940 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC); 941 } 942 MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2; 943 ''' 944 mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp", 945 { "code": mcrr15code, 946 "predicate_test": predicateTest }, []) 947 header_output += McrrOpDeclare.subst(mcrr15Iop) 948 decoder_output += McrrOpConstructor.subst(mcrr15Iop) 949 exec_output += PredOpExecute.subst(mcrr15Iop) 950 951 |
952 enterxCode = ''' 953 NextThumb = true; 954 NextJazelle = true; 955 ''' 956 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 957 { "code": enterxCode, 958 "predicate_test": predicateTest }, []) 959 header_output += BasicDeclare.subst(enterxIop) --- 30 unchanged lines hidden (view full) --- 990 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 991 { "code": clrexCode, 992 "predicate_test": predicateTest },[]) 993 header_output += BasicDeclare.subst(clrexIop) 994 decoder_output += BasicConstructor.subst(clrexIop) 995 exec_output += PredOpExecute.subst(clrexIop) 996 997 isbCode = ''' |
998 // If the barrier is due to a CP15 access check for hyp traps 999 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr, 1000 Hdcr, Hstr, Hcptr, imm)) { 1001 return new HypervisorTrap(machInst, imm, 1002 EC_TRAPPED_CP15_MCR_MRC); 1003 } |
1004 fault = new FlushPipe; 1005 ''' |
1006 isbIop = InstObjParams("isb", "Isb", "ImmOp", |
1007 {"code": isbCode, 1008 "predicate_test": predicateTest}, 1009 ['IsSerializeAfter']) |
1010 header_output += ImmOpDeclare.subst(isbIop) 1011 decoder_output += ImmOpConstructor.subst(isbIop) |
1012 exec_output += PredOpExecute.subst(isbIop) 1013 1014 dsbCode = ''' |
1015 // If the barrier is due to a CP15 access check for hyp traps 1016 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr, 1017 Hdcr, Hstr, Hcptr, imm)) { 1018 return new HypervisorTrap(machInst, imm, 1019 EC_TRAPPED_CP15_MCR_MRC); 1020 } |
1021 fault = new FlushPipe; 1022 ''' |
1023 dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", |
1024 {"code": dsbCode, 1025 "predicate_test": predicateTest}, 1026 ['IsMemBarrier', 'IsSerializeAfter']) |
1027 header_output += ImmOpDeclare.subst(dsbIop) 1028 decoder_output += ImmOpConstructor.subst(dsbIop) |
1029 exec_output += PredOpExecute.subst(dsbIop) 1030 1031 dmbCode = ''' |
1032 // If the barrier is due to a CP15 access check for hyp traps 1033 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr, 1034 Hdcr, Hstr, Hcptr, imm)) { 1035 return new HypervisorTrap(machInst, imm, 1036 EC_TRAPPED_CP15_MCR_MRC); 1037 } |
1038 ''' |
1039 dmbIop = InstObjParams("dmb", "Dmb", "ImmOp", |
1040 {"code": dmbCode, 1041 "predicate_test": predicateTest}, 1042 ['IsMemBarrier']) |
1043 header_output += ImmOpDeclare.subst(dmbIop) 1044 decoder_output += ImmOpConstructor.subst(dmbIop) |
1045 exec_output += PredOpExecute.subst(dmbIop) 1046 1047 dbgCode = ''' 1048 ''' 1049 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 1050 {"code": dbgCode, 1051 "predicate_test": predicateTest}) 1052 header_output += BasicDeclare.subst(dbgIop) --- 36 unchanged lines hidden --- |