1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 46 unchanged lines hidden (view full) --- 55 exec_output = PredOpExecute.subst(svcIop) 56 57}}; 58 59let {{ 60 61 header_output = decoder_output = exec_output = "" 62 |
63 mrsCpsrCode = ''' 64 Dest = (Cpsr | CondCodesF | CondCodesQ | CondCodesGE) & 0xF8FF03DF 65 ''' 66 |
67 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 68 { "code": mrsCpsrCode, 69 "predicate_test": condPredicateTest }, 70 ["IsSerializeBefore"]) 71 header_output += MrsDeclare.subst(mrsCpsrIop) 72 decoder_output += MrsConstructor.subst(mrsCpsrIop) 73 exec_output += PredOpExecute.subst(mrsCpsrIop) 74 --- 4 unchanged lines hidden (view full) --- 79 ["IsSerializeBefore"]) 80 header_output += MrsDeclare.subst(mrsSpsrIop) 81 decoder_output += MrsConstructor.subst(mrsSpsrIop) 82 exec_output += PredOpExecute.subst(mrsSpsrIop) 83 84 msrCpsrRegCode = ''' 85 SCTLR sctlr = Sctlr; 86 uint32_t newCpsr = |
87 cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, Op1, 88 byteMask, false, sctlr.nmfi); |
89 Cpsr = ~CondCodesMask & newCpsr; |
90 CondCodesF = CondCodesMaskF & newCpsr; 91 CondCodesQ = CondCodesMaskQ & newCpsr; 92 CondCodesGE = CondCodesMaskGE & newCpsr; |
93 ''' 94 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 95 { "code": msrCpsrRegCode, 96 "predicate_test": condPredicateTest }, 97 ["IsSerializeAfter","IsNonSpeculative"]) 98 header_output += MsrRegDeclare.subst(msrCpsrRegIop) 99 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 100 exec_output += PredOpExecute.subst(msrCpsrRegIop) --- 5 unchanged lines hidden (view full) --- 106 ["IsSerializeAfter","IsNonSpeculative"]) 107 header_output += MsrRegDeclare.subst(msrSpsrRegIop) 108 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 109 exec_output += PredOpExecute.subst(msrSpsrRegIop) 110 111 msrCpsrImmCode = ''' 112 SCTLR sctlr = Sctlr; 113 uint32_t newCpsr = |
114 cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, imm, 115 byteMask, false, sctlr.nmfi); |
116 Cpsr = ~CondCodesMask & newCpsr; |
117 CondCodesF = CondCodesMaskF & newCpsr; 118 CondCodesQ = CondCodesMaskQ & newCpsr; 119 CondCodesGE = CondCodesMaskGE & newCpsr; |
120 ''' 121 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 122 { "code": msrCpsrImmCode, 123 "predicate_test": condPredicateTest }, 124 ["IsSerializeAfter","IsNonSpeculative"]) 125 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 126 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 127 exec_output += PredOpExecute.subst(msrCpsrImmIop) --- 72 unchanged lines hidden (view full) --- 200 header_output += RegRegOpDeclare.subst(clzIop) 201 decoder_output += RegRegOpConstructor.subst(clzIop) 202 exec_output += PredOpExecute.subst(clzIop) 203 204 ssatCode = ''' 205 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 206 int32_t res; 207 if (satInt(res, operand, imm)) |
208 CondCodesQ = CondCodesQ | (1 << 27); |
209 else |
210 CondCodesQ = CondCodesQ; |
211 Dest = res; 212 ''' 213 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 214 { "code": ssatCode, 215 "predicate_test": condPredicateTest }, []) 216 header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 217 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 218 exec_output += PredOpExecute.subst(ssatIop) 219 220 usatCode = ''' 221 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 222 int32_t res; 223 if (uSatInt(res, operand, imm)) |
224 CondCodesQ = CondCodesQ | (1 << 27); |
225 else |
226 CondCodesQ = CondCodesQ; |
227 Dest = res; 228 ''' 229 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 230 { "code": usatCode, 231 "predicate_test": condPredicateTest }, []) 232 header_output += RegImmRegShiftOpDeclare.subst(usatIop) 233 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 234 exec_output += PredOpExecute.subst(usatIop) 235 236 ssat16Code = ''' 237 int32_t res; 238 uint32_t resTemp = 0; |
239 CondCodesQ = CondCodesQ; |
240 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 241 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 242 if (satInt(res, argLow, imm)) |
243 CondCodesQ = CondCodesQ | (1 << 27); |
244 replaceBits(resTemp, 15, 0, res); 245 if (satInt(res, argHigh, imm)) |
246 CondCodesQ = CondCodesQ | (1 << 27); |
247 replaceBits(resTemp, 31, 16, res); 248 Dest = resTemp; 249 ''' 250 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 251 { "code": ssat16Code, 252 "predicate_test": condPredicateTest }, []) 253 header_output += RegImmRegOpDeclare.subst(ssat16Iop) 254 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 255 exec_output += PredOpExecute.subst(ssat16Iop) 256 257 usat16Code = ''' 258 int32_t res; 259 uint32_t resTemp = 0; |
260 CondCodesQ = CondCodesQ; |
261 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 262 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 263 if (uSatInt(res, argLow, imm)) |
264 CondCodesQ = CondCodesQ | (1 << 27); |
265 replaceBits(resTemp, 15, 0, res); 266 if (uSatInt(res, argHigh, imm)) |
267 CondCodesQ = CondCodesQ | (1 << 27); |
268 replaceBits(resTemp, 31, 16, res); 269 Dest = resTemp; 270 ''' 271 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 272 { "code": usat16Code, 273 "predicate_test": condPredicateTest }, []) 274 header_output += RegImmRegOpDeclare.subst(usat16Iop) 275 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) --- 142 unchanged lines hidden (view full) --- 418 exec_output += PredOpExecute.subst(uxtahIop) 419 420 selCode = ''' 421 uint32_t resTemp = 0; 422 for (unsigned i = 0; i < 4; i++) { 423 int low = i * 8; 424 int high = low + 7; 425 replaceBits(resTemp, high, low, |
426 bits(CondCodesGE, 16 + i) ? |
427 bits(Op1, high, low) : bits(Op2, high, low)); 428 } 429 Dest = resTemp; 430 ''' 431 selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 432 { "code": selCode, 433 "predicate_test": condPredicateTest }, []) 434 header_output += RegRegRegOpDeclare.subst(selIop) --- 348 unchanged lines hidden --- |