1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 69 unchanged lines hidden (view full) --- 78 decoder_output += MrsConstructor.subst(mrsSpsrIop) 79 exec_output += PredOpExecute.subst(mrsSpsrIop) 80 81 msrCpsrRegCode = ''' 82 SCTLR sctlr = Sctlr; 83 uint32_t newCpsr = 84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); 85 Cpsr = ~CondCodesMask & newCpsr; |
86 NextThumb = ((CPSR)newCpsr).t; 87 NextJazelle = ((CPSR)newCpsr).j; |
88 CondCodes = CondCodesMask & newCpsr; 89 ''' 90 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 91 { "code": msrCpsrRegCode, 92 "predicate_test": condPredicateTest }, 93 ["IsSerializeAfter","IsNonSpeculative"]) 94 header_output += MsrRegDeclare.subst(msrCpsrRegIop) 95 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) --- 8 unchanged lines hidden (view full) --- 104 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 105 exec_output += PredOpExecute.subst(msrSpsrRegIop) 106 107 msrCpsrImmCode = ''' 108 SCTLR sctlr = Sctlr; 109 uint32_t newCpsr = 110 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); 111 Cpsr = ~CondCodesMask & newCpsr; |
112 NextThumb = ((CPSR)newCpsr).t; 113 NextJazelle = ((CPSR)newCpsr).j; |
114 CondCodes = CondCodesMask & newCpsr; 115 ''' 116 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 117 { "code": msrCpsrImmCode, 118 "predicate_test": condPredicateTest }, 119 ["IsSerializeAfter","IsNonSpeculative"]) 120 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 121 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) --- 339 unchanged lines hidden (view full) --- 461 ''' 462 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 463 { "code": usada8Code, 464 "predicate_test": predicateTest }, []) 465 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 466 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 467 exec_output += PredOpExecute.subst(usada8Iop) 468 |
469 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' |
470 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst", 471 bkptCode) 472 header_output += BasicDeclare.subst(bkptIop) 473 decoder_output += BasicConstructor.subst(bkptIop) 474 exec_output += BasicExecute.subst(bkptIop) 475 476 nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 477 { "code" : "", "predicate_test" : predicateTest }) --- 160 unchanged lines hidden (view full) --- 638 { "code": "MiscDest = Op1", 639 "predicate_test": predicateTest }, 640 ["IsSerializeAfter","IsNonSpeculative"]) 641 header_output += RegRegOpDeclare.subst(mcr15UserIop) 642 decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 643 exec_output += PredOpExecute.subst(mcr15UserIop) 644 645 enterxCode = ''' |
646 NextThumb = true; 647 NextJazelle = true; |
648 ''' 649 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 650 { "code": enterxCode, 651 "predicate_test": predicateTest }, []) 652 header_output += BasicDeclare.subst(enterxIop) 653 decoder_output += BasicConstructor.subst(enterxIop) 654 exec_output += PredOpExecute.subst(enterxIop) 655 656 leavexCode = ''' |
657 NextThumb = true; 658 NextJazelle = false; |
659 ''' 660 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 661 { "code": leavexCode, 662 "predicate_test": predicateTest }, []) 663 header_output += BasicDeclare.subst(leavexIop) 664 decoder_output += BasicConstructor.subst(leavexIop) 665 exec_output += PredOpExecute.subst(leavexIop) 666 --- 96 unchanged lines hidden --- |