1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 69 unchanged lines hidden (view full) --- 78 decoder_output += MrsConstructor.subst(mrsSpsrIop) 79 exec_output += PredOpExecute.subst(mrsSpsrIop) 80 81 msrCpsrRegCode = ''' 82 SCTLR sctlr = Sctlr; 83 uint32_t newCpsr = 84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); 85 Cpsr = ~CondCodesMask & newCpsr; |
86 ArmISA::PCState pc = PCS; 87 pc.nextThumb(((CPSR)newCpsr).t); 88 pc.nextJazelle(((CPSR)newCpsr).j); 89 PCS = pc; |
90 CondCodes = CondCodesMask & newCpsr; 91 ''' 92 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 93 { "code": msrCpsrRegCode, 94 "predicate_test": condPredicateTest }, 95 ["IsSerializeAfter","IsNonSpeculative"]) 96 header_output += MsrRegDeclare.subst(msrCpsrRegIop) 97 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) --- 8 unchanged lines hidden (view full) --- 106 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 107 exec_output += PredOpExecute.subst(msrSpsrRegIop) 108 109 msrCpsrImmCode = ''' 110 SCTLR sctlr = Sctlr; 111 uint32_t newCpsr = 112 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); 113 Cpsr = ~CondCodesMask & newCpsr; |
114 ArmISA::PCState pc = PCS; 115 pc.nextThumb(((CPSR)newCpsr).t); 116 pc.nextJazelle(((CPSR)newCpsr).j); 117 PCS = pc; |
118 CondCodes = CondCodesMask & newCpsr; 119 ''' 120 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 121 { "code": msrCpsrImmCode, 122 "predicate_test": condPredicateTest }, 123 ["IsSerializeAfter","IsNonSpeculative"]) 124 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 125 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) --- 339 unchanged lines hidden (view full) --- 465 ''' 466 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 467 { "code": usada8Code, 468 "predicate_test": predicateTest }, []) 469 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 470 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 471 exec_output += PredOpExecute.subst(usada8Iop) 472 |
473 bkptCode = ''' 474 ArmISA::PCState pc = PCS; 475 return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent); 476 ''' |
477 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst", |
478 bkptCode) |
479 header_output += BasicDeclare.subst(bkptIop) 480 decoder_output += BasicConstructor.subst(bkptIop) 481 exec_output += BasicExecute.subst(bkptIop) 482 483 nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 484 { "code" : "", "predicate_test" : predicateTest }) 485 header_output += BasicDeclare.subst(nopIop) 486 decoder_output += BasicConstructor.subst(nopIop) --- 158 unchanged lines hidden (view full) --- 645 { "code": "MiscDest = Op1", 646 "predicate_test": predicateTest }, 647 ["IsSerializeAfter","IsNonSpeculative"]) 648 header_output += RegRegOpDeclare.subst(mcr15UserIop) 649 decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 650 exec_output += PredOpExecute.subst(mcr15UserIop) 651 652 enterxCode = ''' |
653 ArmISA::PCState pc = PCS; 654 pc.nextThumb(true); 655 pc.nextJazelle(true); 656 PCS = pc; |
657 ''' 658 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 659 { "code": enterxCode, 660 "predicate_test": predicateTest }, []) 661 header_output += BasicDeclare.subst(enterxIop) 662 decoder_output += BasicConstructor.subst(enterxIop) 663 exec_output += PredOpExecute.subst(enterxIop) 664 665 leavexCode = ''' |
666 ArmISA::PCState pc = PCS; 667 pc.nextThumb(true); 668 pc.nextJazelle(false); 669 PCS = pc; |
670 ''' 671 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 672 { "code": leavexCode, 673 "predicate_test": predicateTest }, []) 674 header_output += BasicDeclare.subst(leavexIop) 675 decoder_output += BasicConstructor.subst(leavexIop) 676 exec_output += PredOpExecute.subst(leavexIop) 677 --- 96 unchanged lines hidden --- |