1// -*- mode:c++ -*-
2
| 1// -*- mode:c++ -*-
2
|
3// Copyright (c) 2010-2012 ARM Limited
| 3// Copyright (c) 2010-2013 ARM Limited
|
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
| 4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
|
43 if (FullSystem) {
44 fault = new SupervisorCall;
45 } else {
46 fault = new SupervisorCall(machInst);
47 }
| 43 fault = new SupervisorCall(machInst, imm);
|
48 '''
49
| 44 '''
45
|
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
| 46 svcIop = InstObjParams("svc", "Svc", "ImmOp",
|
51 { "code": svcCode,
52 "predicate_test": predicateTest },
53 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
| 47 { "code": svcCode,
48 "predicate_test": predicateTest },
49 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
|
54 header_output = BasicDeclare.subst(svcIop)
55 decoder_output = BasicConstructor.subst(svcIop)
| 50 header_output = ImmOpDeclare.subst(svcIop)
51 decoder_output = ImmOpConstructor.subst(svcIop)
|
56 exec_output = PredOpExecute.subst(svcIop)
57
| 52 exec_output = PredOpExecute.subst(svcIop)
53
|
| 54 smcCode = '''
55 HCR hcr = Hcr;
56 CPSR cpsr = Cpsr;
57 SCR scr = Scr;
58
59 if ((cpsr.mode != MODE_USER) && FullSystem) {
60 if (ArmSystem::haveVirtualization(xc->tcBase()) &&
61 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
62 fault = new HypervisorTrap(machInst, 0, EC_SMC_TO_HYP);
63 } else {
64 if (scr.scd) {
65 fault = disabledFault();
66 } else {
67 fault = new SecureMonitorCall(machInst);
68 }
69 }
70 } else {
71 fault = disabledFault();
72 }
73 '''
74
75 smcIop = InstObjParams("smc", "Smc", "PredOp",
76 { "code": smcCode,
77 "predicate_test": predicateTest },
78 ["IsNonSpeculative", "IsSerializeAfter"])
79 header_output += BasicDeclare.subst(smcIop)
80 decoder_output += BasicConstructor.subst(smcIop)
81 exec_output += PredOpExecute.subst(smcIop)
82
83 hvcCode = '''
84 CPSR cpsr = Cpsr;
85 SCR scr = Scr;
86
87 // Filter out the various cases where this instruction isn't defined
88 if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
89 (cpsr.mode == MODE_USER) ||
90 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
91 fault = disabledFault();
92 } else {
93 fault = new HypervisorCall(machInst, imm);
94 }
95 '''
96
97 hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
98 { "code": hvcCode,
99 "predicate_test": predicateTest },
100 ["IsNonSpeculative", "IsSerializeAfter"])
101 header_output += ImmOpDeclare.subst(hvcIop)
102 decoder_output += ImmOpConstructor.subst(hvcIop)
103 exec_output += PredOpExecute.subst(hvcIop)
104
105 eretCode = '''
106 SCTLR sctlr = Sctlr;
107 CPSR old_cpsr = Cpsr;
108 old_cpsr.nz = CondCodesNZ;
109 old_cpsr.c = CondCodesC;
110 old_cpsr.v = CondCodesV;
111 old_cpsr.ge = CondCodesGE;
112
113 CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
114 true, sctlr.nmfi, xc->tcBase());
115 Cpsr = ~CondCodesMask & new_cpsr;
116 CondCodesNZ = new_cpsr.nz;
117 CondCodesC = new_cpsr.c;
118 CondCodesV = new_cpsr.v;
119 CondCodesGE = new_cpsr.ge;
120
121 NextThumb = (new_cpsr).t;
122 NextJazelle = (new_cpsr).j;
123 NextItState = (((new_cpsr).it2 << 2) & 0xFC)
124 | ((new_cpsr).it1 & 0x3);
125
126 NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
127 '''
128
129 eretIop = InstObjParams("eret", "Eret", "PredOp",
130 { "code": eretCode,
131 "predicate_test": predicateTest },
132 ["IsNonSpeculative", "IsSerializeAfter"])
133 header_output += BasicDeclare.subst(eretIop)
134 decoder_output += BasicConstructor.subst(eretIop)
135 exec_output += PredOpExecute.subst(eretIop)
136
137
138
|
58}};
59
60let {{
61
62 header_output = decoder_output = exec_output = ""
63
64 mrsCpsrCode = '''
65 CPSR cpsr = Cpsr;
66 cpsr.nz = CondCodesNZ;
67 cpsr.c = CondCodesC;
68 cpsr.v = CondCodesV;
69 cpsr.ge = CondCodesGE;
70 Dest = cpsr & 0xF8FF03DF
71 '''
72
73 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
74 { "code": mrsCpsrCode,
75 "predicate_test": condPredicateTest },
76 ["IsSerializeBefore"])
77 header_output += MrsDeclare.subst(mrsCpsrIop)
78 decoder_output += MrsConstructor.subst(mrsCpsrIop)
79 exec_output += PredOpExecute.subst(mrsCpsrIop)
80
81 mrsSpsrCode = "Dest = Spsr"
82 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
83 { "code": mrsSpsrCode,
84 "predicate_test": predicateTest },
85 ["IsSerializeBefore"])
86 header_output += MrsDeclare.subst(mrsSpsrIop)
87 decoder_output += MrsConstructor.subst(mrsSpsrIop)
88 exec_output += PredOpExecute.subst(mrsSpsrIop)
89
| 139}};
140
141let {{
142
143 header_output = decoder_output = exec_output = ""
144
145 mrsCpsrCode = '''
146 CPSR cpsr = Cpsr;
147 cpsr.nz = CondCodesNZ;
148 cpsr.c = CondCodesC;
149 cpsr.v = CondCodesV;
150 cpsr.ge = CondCodesGE;
151 Dest = cpsr & 0xF8FF03DF
152 '''
153
154 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
155 { "code": mrsCpsrCode,
156 "predicate_test": condPredicateTest },
157 ["IsSerializeBefore"])
158 header_output += MrsDeclare.subst(mrsCpsrIop)
159 decoder_output += MrsConstructor.subst(mrsCpsrIop)
160 exec_output += PredOpExecute.subst(mrsCpsrIop)
161
162 mrsSpsrCode = "Dest = Spsr"
163 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
164 { "code": mrsSpsrCode,
165 "predicate_test": predicateTest },
166 ["IsSerializeBefore"])
167 header_output += MrsDeclare.subst(mrsSpsrIop)
168 decoder_output += MrsConstructor.subst(mrsSpsrIop)
169 exec_output += PredOpExecute.subst(mrsSpsrIop)
170
|
| 171 mrsBankedRegCode = '''
172 bool isIntReg;
173 int regIdx;
174
175 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
176 if (isIntReg) {
177 Dest = DecodedBankedIntReg;
178 } else {
179 Dest = xc->readMiscReg(regIdx);
180 }
181 } else {
182 return new UndefinedInstruction(machInst, false, mnemonic);
183 }
184 '''
185 mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
186 { "code": mrsBankedRegCode,
187 "predicate_test": predicateTest },
188 ["IsSerializeBefore"])
189 header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
190 decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
191 exec_output += PredOpExecute.subst(mrsBankedRegIop)
192
193 msrBankedRegCode = '''
194 bool isIntReg;
195 int regIdx;
196
197 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
198 if (isIntReg) {
199 // This is a bit nasty, you would have thought that
200 // DecodedBankedIntReg wouldn't be written to unless the
201 // conditions on the IF statements above are met, however if
202 // you look at the generated C code you'll find that they are.
203 // However this is safe as DecodedBankedIntReg (which is used
204 // in operands.isa to get the index of DecodedBankedIntReg)
205 // will return INTREG_DUMMY if its not a valid integer
206 // register, so redirecting the write to somewhere we don't
207 // care about.
208 DecodedBankedIntReg = Op1;
209 } else {
210 xc->setMiscReg(regIdx, Op1);
211 }
212 } else {
213 return new UndefinedInstruction(machInst, false, mnemonic);
214 }
215 '''
216 msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
217 { "code": msrBankedRegCode,
218 "predicate_test": predicateTest },
219 ["IsSerializeAfter"])
220 header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
221 decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
222 exec_output += PredOpExecute.subst(msrBankedRegIop)
223
|
90 msrCpsrRegCode = '''
91 SCTLR sctlr = Sctlr;
92 CPSR old_cpsr = Cpsr;
93 old_cpsr.nz = CondCodesNZ;
94 old_cpsr.c = CondCodesC;
95 old_cpsr.v = CondCodesV;
96 old_cpsr.ge = CondCodesGE;
97
98 CPSR new_cpsr =
| 224 msrCpsrRegCode = '''
225 SCTLR sctlr = Sctlr;
226 CPSR old_cpsr = Cpsr;
227 old_cpsr.nz = CondCodesNZ;
228 old_cpsr.c = CondCodesC;
229 old_cpsr.v = CondCodesV;
230 old_cpsr.ge = CondCodesGE;
231
232 CPSR new_cpsr =
|
99 cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
| 233 cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
234 sctlr.nmfi, xc->tcBase());
|
100 Cpsr = ~CondCodesMask & new_cpsr;
101 CondCodesNZ = new_cpsr.nz;
102 CondCodesC = new_cpsr.c;
103 CondCodesV = new_cpsr.v;
104 CondCodesGE = new_cpsr.ge;
105 '''
106 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
107 { "code": msrCpsrRegCode,
108 "predicate_test": condPredicateTest },
109 ["IsSerializeAfter","IsNonSpeculative"])
110 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
111 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
112 exec_output += PredOpExecute.subst(msrCpsrRegIop)
113
114 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
115 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
116 { "code": msrSpsrRegCode,
117 "predicate_test": predicateTest },
118 ["IsSerializeAfter","IsNonSpeculative"])
119 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
120 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
121 exec_output += PredOpExecute.subst(msrSpsrRegIop)
122
123 msrCpsrImmCode = '''
124 SCTLR sctlr = Sctlr;
125 CPSR old_cpsr = Cpsr;
126 old_cpsr.nz = CondCodesNZ;
127 old_cpsr.c = CondCodesC;
128 old_cpsr.v = CondCodesV;
129 old_cpsr.ge = CondCodesGE;
130 CPSR new_cpsr =
| 235 Cpsr = ~CondCodesMask & new_cpsr;
236 CondCodesNZ = new_cpsr.nz;
237 CondCodesC = new_cpsr.c;
238 CondCodesV = new_cpsr.v;
239 CondCodesGE = new_cpsr.ge;
240 '''
241 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
242 { "code": msrCpsrRegCode,
243 "predicate_test": condPredicateTest },
244 ["IsSerializeAfter","IsNonSpeculative"])
245 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
246 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
247 exec_output += PredOpExecute.subst(msrCpsrRegIop)
248
249 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
250 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
251 { "code": msrSpsrRegCode,
252 "predicate_test": predicateTest },
253 ["IsSerializeAfter","IsNonSpeculative"])
254 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
255 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
256 exec_output += PredOpExecute.subst(msrSpsrRegIop)
257
258 msrCpsrImmCode = '''
259 SCTLR sctlr = Sctlr;
260 CPSR old_cpsr = Cpsr;
261 old_cpsr.nz = CondCodesNZ;
262 old_cpsr.c = CondCodesC;
263 old_cpsr.v = CondCodesV;
264 old_cpsr.ge = CondCodesGE;
265 CPSR new_cpsr =
|
131 cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
| 266 cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
267 sctlr.nmfi, xc->tcBase());
|
132 Cpsr = ~CondCodesMask & new_cpsr;
133 CondCodesNZ = new_cpsr.nz;
134 CondCodesC = new_cpsr.c;
135 CondCodesV = new_cpsr.v;
136 CondCodesGE = new_cpsr.ge;
137 '''
138 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
139 { "code": msrCpsrImmCode,
140 "predicate_test": condPredicateTest },
141 ["IsSerializeAfter","IsNonSpeculative"])
142 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
143 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
144 exec_output += PredOpExecute.subst(msrCpsrImmIop)
145
146 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
147 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
148 { "code": msrSpsrImmCode,
149 "predicate_test": predicateTest },
150 ["IsSerializeAfter","IsNonSpeculative"])
151 header_output += MsrImmDeclare.subst(msrSpsrImmIop)
152 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
153 exec_output += PredOpExecute.subst(msrSpsrImmIop)
154
155 revCode = '''
156 uint32_t val = Op1;
157 Dest = swap_byte(val);
158 '''
159 revIop = InstObjParams("rev", "Rev", "RegRegOp",
160 { "code": revCode,
161 "predicate_test": predicateTest }, [])
162 header_output += RegRegOpDeclare.subst(revIop)
163 decoder_output += RegRegOpConstructor.subst(revIop)
164 exec_output += PredOpExecute.subst(revIop)
165
166 rev16Code = '''
167 uint32_t val = Op1;
168 Dest = (bits(val, 15, 8) << 0) |
169 (bits(val, 7, 0) << 8) |
170 (bits(val, 31, 24) << 16) |
171 (bits(val, 23, 16) << 24);
172 '''
173 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
174 { "code": rev16Code,
175 "predicate_test": predicateTest }, [])
176 header_output += RegRegOpDeclare.subst(rev16Iop)
177 decoder_output += RegRegOpConstructor.subst(rev16Iop)
178 exec_output += PredOpExecute.subst(rev16Iop)
179
180 revshCode = '''
181 uint16_t val = Op1;
182 Dest = sext<16>(swap_byte(val));
183 '''
184 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
185 { "code": revshCode,
186 "predicate_test": predicateTest }, [])
187 header_output += RegRegOpDeclare.subst(revshIop)
188 decoder_output += RegRegOpConstructor.subst(revshIop)
189 exec_output += PredOpExecute.subst(revshIop)
190
191 rbitCode = '''
192 uint8_t *opBytes = (uint8_t *)&Op1;
193 uint32_t resTemp;
194 uint8_t *destBytes = (uint8_t *)&resTemp;
195 // This reverses the bytes and bits of the input, or so says the
196 // internet.
197 for (int i = 0; i < 4; i++) {
198 uint32_t temp = opBytes[i];
199 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
200 destBytes[3 - i] = (temp * 0x10101) >> 16;
201 }
202 Dest = resTemp;
203 '''
204 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
205 { "code": rbitCode,
206 "predicate_test": predicateTest }, [])
207 header_output += RegRegOpDeclare.subst(rbitIop)
208 decoder_output += RegRegOpConstructor.subst(rbitIop)
209 exec_output += PredOpExecute.subst(rbitIop)
210
211 clzCode = '''
212 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
213 '''
214 clzIop = InstObjParams("clz", "Clz", "RegRegOp",
215 { "code": clzCode,
216 "predicate_test": predicateTest }, [])
217 header_output += RegRegOpDeclare.subst(clzIop)
218 decoder_output += RegRegOpConstructor.subst(clzIop)
219 exec_output += PredOpExecute.subst(clzIop)
220
221 ssatCode = '''
222 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
223 int32_t res;
224 if (satInt(res, operand, imm))
225 CpsrQ = 1 << 27;
226 Dest = res;
227 '''
228 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
229 { "code": ssatCode,
230 "predicate_test": pickPredicate(ssatCode) }, [])
231 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
232 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
233 exec_output += PredOpExecute.subst(ssatIop)
234
235 usatCode = '''
236 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
237 int32_t res;
238 if (uSatInt(res, operand, imm))
239 CpsrQ = 1 << 27;
240 Dest = res;
241 '''
242 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
243 { "code": usatCode,
244 "predicate_test": pickPredicate(usatCode) }, [])
245 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
246 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
247 exec_output += PredOpExecute.subst(usatIop)
248
249 ssat16Code = '''
250 int32_t res;
251 uint32_t resTemp = 0;
252 int32_t argLow = sext<16>(bits(Op1, 15, 0));
253 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
254 if (satInt(res, argLow, imm))
255 CpsrQ = 1 << 27;
256 replaceBits(resTemp, 15, 0, res);
257 if (satInt(res, argHigh, imm))
258 CpsrQ = 1 << 27;
259 replaceBits(resTemp, 31, 16, res);
260 Dest = resTemp;
261 '''
262 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
263 { "code": ssat16Code,
264 "predicate_test": pickPredicate(ssat16Code) }, [])
265 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
266 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
267 exec_output += PredOpExecute.subst(ssat16Iop)
268
269 usat16Code = '''
270 int32_t res;
271 uint32_t resTemp = 0;
272 int32_t argLow = sext<16>(bits(Op1, 15, 0));
273 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
274 if (uSatInt(res, argLow, imm))
275 CpsrQ = 1 << 27;
276 replaceBits(resTemp, 15, 0, res);
277 if (uSatInt(res, argHigh, imm))
278 CpsrQ = 1 << 27;
279 replaceBits(resTemp, 31, 16, res);
280 Dest = resTemp;
281 '''
282 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
283 { "code": usat16Code,
284 "predicate_test": pickPredicate(usat16Code) }, [])
285 header_output += RegImmRegOpDeclare.subst(usat16Iop)
286 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
287 exec_output += PredOpExecute.subst(usat16Iop)
288
289 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
290 { "code":
291 "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
292 "predicate_test": predicateTest }, [])
293 header_output += RegImmRegOpDeclare.subst(sxtbIop)
294 decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
295 exec_output += PredOpExecute.subst(sxtbIop)
296
297 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
298 { "code":
299 '''
300 Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
301 Op1;
302 ''',
303 "predicate_test": predicateTest }, [])
304 header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
305 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
306 exec_output += PredOpExecute.subst(sxtabIop)
307
308 sxtb16Code = '''
309 uint32_t resTemp = 0;
310 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
311 replaceBits(resTemp, 31, 16,
312 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
313 Dest = resTemp;
314 '''
315 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
316 { "code": sxtb16Code,
317 "predicate_test": predicateTest }, [])
318 header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
319 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
320 exec_output += PredOpExecute.subst(sxtb16Iop)
321
322 sxtab16Code = '''
323 uint32_t resTemp = 0;
324 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
325 bits(Op1, 15, 0));
326 replaceBits(resTemp, 31, 16,
327 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
328 bits(Op1, 31, 16));
329 Dest = resTemp;
330 '''
331 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
332 { "code": sxtab16Code,
333 "predicate_test": predicateTest }, [])
334 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
335 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
336 exec_output += PredOpExecute.subst(sxtab16Iop)
337
338 sxthCode = '''
339 uint64_t rotated = (uint32_t)Op1;
340 rotated = (rotated | (rotated << 32)) >> imm;
341 Dest = sext<16>((uint16_t)rotated);
342 '''
343 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
344 { "code": sxthCode,
345 "predicate_test": predicateTest }, [])
346 header_output += RegImmRegOpDeclare.subst(sxthIop)
347 decoder_output += RegImmRegOpConstructor.subst(sxthIop)
348 exec_output += PredOpExecute.subst(sxthIop)
349
350 sxtahCode = '''
351 uint64_t rotated = (uint32_t)Op2;
352 rotated = (rotated | (rotated << 32)) >> imm;
353 Dest = sext<16>((uint16_t)rotated) + Op1;
354 '''
355 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
356 { "code": sxtahCode,
357 "predicate_test": predicateTest }, [])
358 header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
359 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
360 exec_output += PredOpExecute.subst(sxtahIop)
361
362 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
363 { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
364 "predicate_test": predicateTest }, [])
365 header_output += RegImmRegOpDeclare.subst(uxtbIop)
366 decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
367 exec_output += PredOpExecute.subst(uxtbIop)
368
369 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
370 { "code":
371 "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
372 "predicate_test": predicateTest }, [])
373 header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
374 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
375 exec_output += PredOpExecute.subst(uxtabIop)
376
377 uxtb16Code = '''
378 uint32_t resTemp = 0;
379 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
380 replaceBits(resTemp, 31, 16,
381 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
382 Dest = resTemp;
383 '''
384 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
385 { "code": uxtb16Code,
386 "predicate_test": predicateTest }, [])
387 header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
388 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
389 exec_output += PredOpExecute.subst(uxtb16Iop)
390
391 uxtab16Code = '''
392 uint32_t resTemp = 0;
393 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
394 bits(Op1, 15, 0));
395 replaceBits(resTemp, 31, 16,
396 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
397 bits(Op1, 31, 16));
398 Dest = resTemp;
399 '''
400 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
401 { "code": uxtab16Code,
402 "predicate_test": predicateTest }, [])
403 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
404 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
405 exec_output += PredOpExecute.subst(uxtab16Iop)
406
407 uxthCode = '''
408 uint64_t rotated = (uint32_t)Op1;
409 rotated = (rotated | (rotated << 32)) >> imm;
410 Dest = (uint16_t)rotated;
411 '''
412 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
413 { "code": uxthCode,
414 "predicate_test": predicateTest }, [])
415 header_output += RegImmRegOpDeclare.subst(uxthIop)
416 decoder_output += RegImmRegOpConstructor.subst(uxthIop)
417 exec_output += PredOpExecute.subst(uxthIop)
418
419 uxtahCode = '''
420 uint64_t rotated = (uint32_t)Op2;
421 rotated = (rotated | (rotated << 32)) >> imm;
422 Dest = (uint16_t)rotated + Op1;
423 '''
424 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
425 { "code": uxtahCode,
426 "predicate_test": predicateTest }, [])
427 header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
428 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
429 exec_output += PredOpExecute.subst(uxtahIop)
430
431 selCode = '''
432 uint32_t resTemp = 0;
433 for (unsigned i = 0; i < 4; i++) {
434 int low = i * 8;
435 int high = low + 7;
436 replaceBits(resTemp, high, low,
437 bits(CondCodesGE, i) ?
438 bits(Op1, high, low) : bits(Op2, high, low));
439 }
440 Dest = resTemp;
441 '''
442 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
443 { "code": selCode,
444 "predicate_test": predicateTest }, [])
445 header_output += RegRegRegOpDeclare.subst(selIop)
446 decoder_output += RegRegRegOpConstructor.subst(selIop)
447 exec_output += PredOpExecute.subst(selIop)
448
449 usad8Code = '''
450 uint32_t resTemp = 0;
451 for (unsigned i = 0; i < 4; i++) {
452 int low = i * 8;
453 int high = low + 7;
454 int32_t diff = bits(Op1, high, low) -
455 bits(Op2, high, low);
456 resTemp += ((diff < 0) ? -diff : diff);
457 }
458 Dest = resTemp;
459 '''
460 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
461 { "code": usad8Code,
462 "predicate_test": predicateTest }, [])
463 header_output += RegRegRegOpDeclare.subst(usad8Iop)
464 decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
465 exec_output += PredOpExecute.subst(usad8Iop)
466
467 usada8Code = '''
468 uint32_t resTemp = 0;
469 for (unsigned i = 0; i < 4; i++) {
470 int low = i * 8;
471 int high = low + 7;
472 int32_t diff = bits(Op1, high, low) -
473 bits(Op2, high, low);
474 resTemp += ((diff < 0) ? -diff : diff);
475 }
476 Dest = Op3 + resTemp;
477 '''
478 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
479 { "code": usada8Code,
480 "predicate_test": predicateTest }, [])
481 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
482 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
483 exec_output += PredOpExecute.subst(usada8Iop)
484
485 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
486 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
487 header_output += BasicDeclare.subst(bkptIop)
488 decoder_output += BasicConstructor.subst(bkptIop)
489 exec_output += BasicExecute.subst(bkptIop)
490
| 268 Cpsr = ~CondCodesMask & new_cpsr;
269 CondCodesNZ = new_cpsr.nz;
270 CondCodesC = new_cpsr.c;
271 CondCodesV = new_cpsr.v;
272 CondCodesGE = new_cpsr.ge;
273 '''
274 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
275 { "code": msrCpsrImmCode,
276 "predicate_test": condPredicateTest },
277 ["IsSerializeAfter","IsNonSpeculative"])
278 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
279 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
280 exec_output += PredOpExecute.subst(msrCpsrImmIop)
281
282 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
283 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
284 { "code": msrSpsrImmCode,
285 "predicate_test": predicateTest },
286 ["IsSerializeAfter","IsNonSpeculative"])
287 header_output += MsrImmDeclare.subst(msrSpsrImmIop)
288 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
289 exec_output += PredOpExecute.subst(msrSpsrImmIop)
290
291 revCode = '''
292 uint32_t val = Op1;
293 Dest = swap_byte(val);
294 '''
295 revIop = InstObjParams("rev", "Rev", "RegRegOp",
296 { "code": revCode,
297 "predicate_test": predicateTest }, [])
298 header_output += RegRegOpDeclare.subst(revIop)
299 decoder_output += RegRegOpConstructor.subst(revIop)
300 exec_output += PredOpExecute.subst(revIop)
301
302 rev16Code = '''
303 uint32_t val = Op1;
304 Dest = (bits(val, 15, 8) << 0) |
305 (bits(val, 7, 0) << 8) |
306 (bits(val, 31, 24) << 16) |
307 (bits(val, 23, 16) << 24);
308 '''
309 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
310 { "code": rev16Code,
311 "predicate_test": predicateTest }, [])
312 header_output += RegRegOpDeclare.subst(rev16Iop)
313 decoder_output += RegRegOpConstructor.subst(rev16Iop)
314 exec_output += PredOpExecute.subst(rev16Iop)
315
316 revshCode = '''
317 uint16_t val = Op1;
318 Dest = sext<16>(swap_byte(val));
319 '''
320 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
321 { "code": revshCode,
322 "predicate_test": predicateTest }, [])
323 header_output += RegRegOpDeclare.subst(revshIop)
324 decoder_output += RegRegOpConstructor.subst(revshIop)
325 exec_output += PredOpExecute.subst(revshIop)
326
327 rbitCode = '''
328 uint8_t *opBytes = (uint8_t *)&Op1;
329 uint32_t resTemp;
330 uint8_t *destBytes = (uint8_t *)&resTemp;
331 // This reverses the bytes and bits of the input, or so says the
332 // internet.
333 for (int i = 0; i < 4; i++) {
334 uint32_t temp = opBytes[i];
335 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
336 destBytes[3 - i] = (temp * 0x10101) >> 16;
337 }
338 Dest = resTemp;
339 '''
340 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
341 { "code": rbitCode,
342 "predicate_test": predicateTest }, [])
343 header_output += RegRegOpDeclare.subst(rbitIop)
344 decoder_output += RegRegOpConstructor.subst(rbitIop)
345 exec_output += PredOpExecute.subst(rbitIop)
346
347 clzCode = '''
348 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
349 '''
350 clzIop = InstObjParams("clz", "Clz", "RegRegOp",
351 { "code": clzCode,
352 "predicate_test": predicateTest }, [])
353 header_output += RegRegOpDeclare.subst(clzIop)
354 decoder_output += RegRegOpConstructor.subst(clzIop)
355 exec_output += PredOpExecute.subst(clzIop)
356
357 ssatCode = '''
358 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
359 int32_t res;
360 if (satInt(res, operand, imm))
361 CpsrQ = 1 << 27;
362 Dest = res;
363 '''
364 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
365 { "code": ssatCode,
366 "predicate_test": pickPredicate(ssatCode) }, [])
367 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
368 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
369 exec_output += PredOpExecute.subst(ssatIop)
370
371 usatCode = '''
372 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
373 int32_t res;
374 if (uSatInt(res, operand, imm))
375 CpsrQ = 1 << 27;
376 Dest = res;
377 '''
378 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
379 { "code": usatCode,
380 "predicate_test": pickPredicate(usatCode) }, [])
381 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
382 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
383 exec_output += PredOpExecute.subst(usatIop)
384
385 ssat16Code = '''
386 int32_t res;
387 uint32_t resTemp = 0;
388 int32_t argLow = sext<16>(bits(Op1, 15, 0));
389 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
390 if (satInt(res, argLow, imm))
391 CpsrQ = 1 << 27;
392 replaceBits(resTemp, 15, 0, res);
393 if (satInt(res, argHigh, imm))
394 CpsrQ = 1 << 27;
395 replaceBits(resTemp, 31, 16, res);
396 Dest = resTemp;
397 '''
398 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
399 { "code": ssat16Code,
400 "predicate_test": pickPredicate(ssat16Code) }, [])
401 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
402 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
403 exec_output += PredOpExecute.subst(ssat16Iop)
404
405 usat16Code = '''
406 int32_t res;
407 uint32_t resTemp = 0;
408 int32_t argLow = sext<16>(bits(Op1, 15, 0));
409 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
410 if (uSatInt(res, argLow, imm))
411 CpsrQ = 1 << 27;
412 replaceBits(resTemp, 15, 0, res);
413 if (uSatInt(res, argHigh, imm))
414 CpsrQ = 1 << 27;
415 replaceBits(resTemp, 31, 16, res);
416 Dest = resTemp;
417 '''
418 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
419 { "code": usat16Code,
420 "predicate_test": pickPredicate(usat16Code) }, [])
421 header_output += RegImmRegOpDeclare.subst(usat16Iop)
422 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
423 exec_output += PredOpExecute.subst(usat16Iop)
424
425 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
426 { "code":
427 "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
428 "predicate_test": predicateTest }, [])
429 header_output += RegImmRegOpDeclare.subst(sxtbIop)
430 decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
431 exec_output += PredOpExecute.subst(sxtbIop)
432
433 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
434 { "code":
435 '''
436 Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
437 Op1;
438 ''',
439 "predicate_test": predicateTest }, [])
440 header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
441 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
442 exec_output += PredOpExecute.subst(sxtabIop)
443
444 sxtb16Code = '''
445 uint32_t resTemp = 0;
446 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
447 replaceBits(resTemp, 31, 16,
448 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
449 Dest = resTemp;
450 '''
451 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
452 { "code": sxtb16Code,
453 "predicate_test": predicateTest }, [])
454 header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
455 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
456 exec_output += PredOpExecute.subst(sxtb16Iop)
457
458 sxtab16Code = '''
459 uint32_t resTemp = 0;
460 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
461 bits(Op1, 15, 0));
462 replaceBits(resTemp, 31, 16,
463 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
464 bits(Op1, 31, 16));
465 Dest = resTemp;
466 '''
467 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
468 { "code": sxtab16Code,
469 "predicate_test": predicateTest }, [])
470 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
471 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
472 exec_output += PredOpExecute.subst(sxtab16Iop)
473
474 sxthCode = '''
475 uint64_t rotated = (uint32_t)Op1;
476 rotated = (rotated | (rotated << 32)) >> imm;
477 Dest = sext<16>((uint16_t)rotated);
478 '''
479 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
480 { "code": sxthCode,
481 "predicate_test": predicateTest }, [])
482 header_output += RegImmRegOpDeclare.subst(sxthIop)
483 decoder_output += RegImmRegOpConstructor.subst(sxthIop)
484 exec_output += PredOpExecute.subst(sxthIop)
485
486 sxtahCode = '''
487 uint64_t rotated = (uint32_t)Op2;
488 rotated = (rotated | (rotated << 32)) >> imm;
489 Dest = sext<16>((uint16_t)rotated) + Op1;
490 '''
491 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
492 { "code": sxtahCode,
493 "predicate_test": predicateTest }, [])
494 header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
495 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
496 exec_output += PredOpExecute.subst(sxtahIop)
497
498 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
499 { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
500 "predicate_test": predicateTest }, [])
501 header_output += RegImmRegOpDeclare.subst(uxtbIop)
502 decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
503 exec_output += PredOpExecute.subst(uxtbIop)
504
505 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
506 { "code":
507 "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
508 "predicate_test": predicateTest }, [])
509 header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
510 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
511 exec_output += PredOpExecute.subst(uxtabIop)
512
513 uxtb16Code = '''
514 uint32_t resTemp = 0;
515 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
516 replaceBits(resTemp, 31, 16,
517 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
518 Dest = resTemp;
519 '''
520 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
521 { "code": uxtb16Code,
522 "predicate_test": predicateTest }, [])
523 header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
524 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
525 exec_output += PredOpExecute.subst(uxtb16Iop)
526
527 uxtab16Code = '''
528 uint32_t resTemp = 0;
529 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
530 bits(Op1, 15, 0));
531 replaceBits(resTemp, 31, 16,
532 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
533 bits(Op1, 31, 16));
534 Dest = resTemp;
535 '''
536 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
537 { "code": uxtab16Code,
538 "predicate_test": predicateTest }, [])
539 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
540 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
541 exec_output += PredOpExecute.subst(uxtab16Iop)
542
543 uxthCode = '''
544 uint64_t rotated = (uint32_t)Op1;
545 rotated = (rotated | (rotated << 32)) >> imm;
546 Dest = (uint16_t)rotated;
547 '''
548 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
549 { "code": uxthCode,
550 "predicate_test": predicateTest }, [])
551 header_output += RegImmRegOpDeclare.subst(uxthIop)
552 decoder_output += RegImmRegOpConstructor.subst(uxthIop)
553 exec_output += PredOpExecute.subst(uxthIop)
554
555 uxtahCode = '''
556 uint64_t rotated = (uint32_t)Op2;
557 rotated = (rotated | (rotated << 32)) >> imm;
558 Dest = (uint16_t)rotated + Op1;
559 '''
560 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
561 { "code": uxtahCode,
562 "predicate_test": predicateTest }, [])
563 header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
564 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
565 exec_output += PredOpExecute.subst(uxtahIop)
566
567 selCode = '''
568 uint32_t resTemp = 0;
569 for (unsigned i = 0; i < 4; i++) {
570 int low = i * 8;
571 int high = low + 7;
572 replaceBits(resTemp, high, low,
573 bits(CondCodesGE, i) ?
574 bits(Op1, high, low) : bits(Op2, high, low));
575 }
576 Dest = resTemp;
577 '''
578 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
579 { "code": selCode,
580 "predicate_test": predicateTest }, [])
581 header_output += RegRegRegOpDeclare.subst(selIop)
582 decoder_output += RegRegRegOpConstructor.subst(selIop)
583 exec_output += PredOpExecute.subst(selIop)
584
585 usad8Code = '''
586 uint32_t resTemp = 0;
587 for (unsigned i = 0; i < 4; i++) {
588 int low = i * 8;
589 int high = low + 7;
590 int32_t diff = bits(Op1, high, low) -
591 bits(Op2, high, low);
592 resTemp += ((diff < 0) ? -diff : diff);
593 }
594 Dest = resTemp;
595 '''
596 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
597 { "code": usad8Code,
598 "predicate_test": predicateTest }, [])
599 header_output += RegRegRegOpDeclare.subst(usad8Iop)
600 decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
601 exec_output += PredOpExecute.subst(usad8Iop)
602
603 usada8Code = '''
604 uint32_t resTemp = 0;
605 for (unsigned i = 0; i < 4; i++) {
606 int low = i * 8;
607 int high = low + 7;
608 int32_t diff = bits(Op1, high, low) -
609 bits(Op2, high, low);
610 resTemp += ((diff < 0) ? -diff : diff);
611 }
612 Dest = Op3 + resTemp;
613 '''
614 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
615 { "code": usada8Code,
616 "predicate_test": predicateTest }, [])
617 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
618 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
619 exec_output += PredOpExecute.subst(usada8Iop)
620
621 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
622 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
623 header_output += BasicDeclare.subst(bkptIop)
624 decoder_output += BasicConstructor.subst(bkptIop)
625 exec_output += BasicExecute.subst(bkptIop)
626
|
491 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
492 { "code" : "", "predicate_test" : predicateTest },
493 ['IsNop'])
| 627 nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
|
494 header_output += BasicDeclare.subst(nopIop)
| 628 header_output += BasicDeclare.subst(nopIop)
|
495 decoder_output += BasicConstructor.subst(nopIop)
496 exec_output += PredOpExecute.subst(nopIop)
| 629 decoder_output += BasicConstructor64.subst(nopIop)
630 exec_output += BasicExecute.subst(nopIop)
|
497
498 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
499 { "code" : "", "predicate_test" : predicateTest })
500 header_output += BasicDeclare.subst(yieldIop)
501 decoder_output += BasicConstructor.subst(yieldIop)
502 exec_output += PredOpExecute.subst(yieldIop)
503
504 wfeCode = '''
| 631
632 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
633 { "code" : "", "predicate_test" : predicateTest })
634 header_output += BasicDeclare.subst(yieldIop)
635 decoder_output += BasicConstructor.subst(yieldIop)
636 exec_output += PredOpExecute.subst(yieldIop)
637
638 wfeCode = '''
|
505 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
| 639 HCR hcr = Hcr;
640 CPSR cpsr = Cpsr;
641 SCR scr = Scr64;
642 SCTLR sctlr = Sctlr;
643
644 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
645 ThreadContext *tc = xc->tcBase();
|
506 if (SevMailbox == 1) {
507 SevMailbox = 0;
| 646 if (SevMailbox == 1) {
647 SevMailbox = 0;
|
508 PseudoInst::quiesceSkip(xc->tcBase());
509 } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
510 PseudoInst::quiesceSkip(xc->tcBase());
| 648 PseudoInst::quiesceSkip(tc);
649 } else if (tc->getCpuPtr()->getInterruptController()->checkInterrupts(tc)) {
650 PseudoInst::quiesceSkip(tc);
651 } else if (cpsr.el == EL0 && !sctlr.ntwe) {
652 PseudoInst::quiesceSkip(tc);
653 fault = new SupervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE);
654 } else if (ArmSystem::haveVirtualization(tc) &&
655 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) &&
656 hcr.twe) {
657 PseudoInst::quiesceSkip(tc);
658 fault = new HypervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE);
659 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twe) {
660 PseudoInst::quiesceSkip(tc);
661 fault = new SecureMonitorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE);
|
511 } else {
| 662 } else {
|
512 PseudoInst::quiesce(xc->tcBase());
| 663 PseudoInst::quiesce(tc);
|
513 }
514 '''
515 wfePredFixUpCode = '''
516 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
517 // and SEV interrupts
518 SevMailbox = 1;
519 '''
520 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
521 { "code" : wfeCode,
522 "pred_fixup" : wfePredFixUpCode,
523 "predicate_test" : predicateTest },
524 ["IsNonSpeculative", "IsQuiesce",
525 "IsSerializeAfter", "IsUnverifiable"])
526 header_output += BasicDeclare.subst(wfeIop)
527 decoder_output += BasicConstructor.subst(wfeIop)
528 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
529
530 wfiCode = '''
| 664 }
665 '''
666 wfePredFixUpCode = '''
667 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
668 // and SEV interrupts
669 SevMailbox = 1;
670 '''
671 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
672 { "code" : wfeCode,
673 "pred_fixup" : wfePredFixUpCode,
674 "predicate_test" : predicateTest },
675 ["IsNonSpeculative", "IsQuiesce",
676 "IsSerializeAfter", "IsUnverifiable"])
677 header_output += BasicDeclare.subst(wfeIop)
678 decoder_output += BasicConstructor.subst(wfeIop)
679 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
680
681 wfiCode = '''
|
| 682 HCR hcr = Hcr;
683 CPSR cpsr = Cpsr;
684 SCR scr = Scr64;
685 SCTLR sctlr = Sctlr;
686
|
531 // WFI doesn't sleep if interrupts are pending (masked or not)
| 687 // WFI doesn't sleep if interrupts are pending (masked or not)
|
532 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
533 PseudoInst::quiesceSkip(xc->tcBase());
| 688 ThreadContext *tc = xc->tcBase();
689 if (tc->getCpuPtr()->getInterruptController()->checkWfiWake(hcr, cpsr,
690 scr)) {
691 PseudoInst::quiesceSkip(tc);
692 } else if (cpsr.el == EL0 && !sctlr.ntwi) {
693 PseudoInst::quiesceSkip(tc);
694 fault = new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE);
695 } else if (ArmSystem::haveVirtualization(tc) && hcr.twi &&
696 (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) {
697 PseudoInst::quiesceSkip(tc);
698 fault = new HypervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE);
699 } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) {
700 PseudoInst::quiesceSkip(tc);
701 fault = new SecureMonitorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE);
|
534 } else {
| 702 } else {
|
535 PseudoInst::quiesce(xc->tcBase());
| 703 PseudoInst::quiesce(tc);
|
536 }
| 704 }
|
| 705 tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
|
537 '''
538 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
539 { "code" : wfiCode, "predicate_test" : predicateTest },
540 ["IsNonSpeculative", "IsQuiesce",
541 "IsSerializeAfter", "IsUnverifiable"])
542 header_output += BasicDeclare.subst(wfiIop)
543 decoder_output += BasicConstructor.subst(wfiIop)
544 exec_output += QuiescePredOpExecute.subst(wfiIop)
545
546 sevCode = '''
547 SevMailbox = 1;
548 System *sys = xc->tcBase()->getSystemPtr();
549 for (int x = 0; x < sys->numContexts(); x++) {
550 ThreadContext *oc = sys->getThreadContext(x);
551 if (oc == xc->tcBase())
552 continue;
553 // Wake CPU with interrupt if they were sleeping
554 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
555 // Post Interrupt and wake cpu if needed
556 oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
557 }
558 }
559 '''
560 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
561 { "code" : sevCode, "predicate_test" : predicateTest },
562 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
563 header_output += BasicDeclare.subst(sevIop)
564 decoder_output += BasicConstructor.subst(sevIop)
565 exec_output += PredOpExecute.subst(sevIop)
566
| 706 '''
707 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
708 { "code" : wfiCode, "predicate_test" : predicateTest },
709 ["IsNonSpeculative", "IsQuiesce",
710 "IsSerializeAfter", "IsUnverifiable"])
711 header_output += BasicDeclare.subst(wfiIop)
712 decoder_output += BasicConstructor.subst(wfiIop)
713 exec_output += QuiescePredOpExecute.subst(wfiIop)
714
715 sevCode = '''
716 SevMailbox = 1;
717 System *sys = xc->tcBase()->getSystemPtr();
718 for (int x = 0; x < sys->numContexts(); x++) {
719 ThreadContext *oc = sys->getThreadContext(x);
720 if (oc == xc->tcBase())
721 continue;
722 // Wake CPU with interrupt if they were sleeping
723 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
724 // Post Interrupt and wake cpu if needed
725 oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
726 }
727 }
728 '''
729 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
730 { "code" : sevCode, "predicate_test" : predicateTest },
731 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
732 header_output += BasicDeclare.subst(sevIop)
733 decoder_output += BasicConstructor.subst(sevIop)
734 exec_output += PredOpExecute.subst(sevIop)
735
|
| 736 sevlCode = '''
737 SevMailbox = 1;
738 '''
739 sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
740 { "code" : sevlCode, "predicate_test" : predicateTest },
741 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
742 header_output += BasicDeclare.subst(sevlIop)
743 decoder_output += BasicConstructor.subst(sevlIop)
744 exec_output += BasicExecute.subst(sevlIop)
745
|
567 itIop = InstObjParams("it", "ItInst", "PredOp", \
568 { "code" : ";",
569 "predicate_test" : predicateTest }, [])
570 header_output += BasicDeclare.subst(itIop)
571 decoder_output += BasicConstructor.subst(itIop)
572 exec_output += PredOpExecute.subst(itIop)
573 unknownCode = '''
| 746 itIop = InstObjParams("it", "ItInst", "PredOp", \
747 { "code" : ";",
748 "predicate_test" : predicateTest }, [])
749 header_output += BasicDeclare.subst(itIop)
750 decoder_output += BasicConstructor.subst(itIop)
751 exec_output += PredOpExecute.subst(itIop)
752 unknownCode = '''
|
574 if (FullSystem)
575 return new UndefinedInstruction;
576 else
577 return new UndefinedInstruction(machInst, true);
| 753 return new UndefinedInstruction(machInst, true);
|
578 '''
579 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
580 { "code": unknownCode,
581 "predicate_test": predicateTest })
582 header_output += BasicDeclare.subst(unknownIop)
583 decoder_output += BasicConstructor.subst(unknownIop)
584 exec_output += PredOpExecute.subst(unknownIop)
585
586 ubfxCode = '''
587 Dest = bits(Op1, imm2, imm1);
588 '''
589 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
590 { "code": ubfxCode,
591 "predicate_test": predicateTest }, [])
592 header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
593 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
594 exec_output += PredOpExecute.subst(ubfxIop)
595
596 sbfxCode = '''
597 int32_t resTemp = bits(Op1, imm2, imm1);
598 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
599 '''
600 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
601 { "code": sbfxCode,
602 "predicate_test": predicateTest }, [])
603 header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
604 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
605 exec_output += PredOpExecute.subst(sbfxIop)
606
607 bfcCode = '''
608 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
609 '''
610 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
611 { "code": bfcCode,
612 "predicate_test": predicateTest }, [])
613 header_output += RegRegImmImmOpDeclare.subst(bfcIop)
614 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
615 exec_output += PredOpExecute.subst(bfcIop)
616
617 bfiCode = '''
618 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
619 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
620 '''
621 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
622 { "code": bfiCode,
623 "predicate_test": predicateTest }, [])
624 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
625 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
626 exec_output += PredOpExecute.subst(bfiIop)
627
628 mrc14code = '''
| 754 '''
755 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
756 { "code": unknownCode,
757 "predicate_test": predicateTest })
758 header_output += BasicDeclare.subst(unknownIop)
759 decoder_output += BasicConstructor.subst(unknownIop)
760 exec_output += PredOpExecute.subst(unknownIop)
761
762 ubfxCode = '''
763 Dest = bits(Op1, imm2, imm1);
764 '''
765 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
766 { "code": ubfxCode,
767 "predicate_test": predicateTest }, [])
768 header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
769 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
770 exec_output += PredOpExecute.subst(ubfxIop)
771
772 sbfxCode = '''
773 int32_t resTemp = bits(Op1, imm2, imm1);
774 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
775 '''
776 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
777 { "code": sbfxCode,
778 "predicate_test": predicateTest }, [])
779 header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
780 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
781 exec_output += PredOpExecute.subst(sbfxIop)
782
783 bfcCode = '''
784 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
785 '''
786 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
787 { "code": bfcCode,
788 "predicate_test": predicateTest }, [])
789 header_output += RegRegImmImmOpDeclare.subst(bfcIop)
790 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
791 exec_output += PredOpExecute.subst(bfcIop)
792
793 bfiCode = '''
794 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
795 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
796 '''
797 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
798 { "code": bfiCode,
799 "predicate_test": predicateTest }, [])
800 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
801 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
802 exec_output += PredOpExecute.subst(bfiIop)
803
804 mrc14code = '''
|
629 CPSR cpsr = Cpsr;
630 if (cpsr.mode == MODE_USER) {
631 if (FullSystem)
632 return new UndefinedInstruction;
633 else
634 return new UndefinedInstruction(false, mnemonic);
| 805 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1);
806 if (!canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) {
807 return new UndefinedInstruction(machInst, false, mnemonic);
|
635 }
| 808 }
|
| 809 if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
810 Hstr, Hcptr, imm)) {
811 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC);
812 }
|
636 Dest = MiscOp1;
637 '''
638
| 813 Dest = MiscOp1;
814 '''
815
|
639 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegOp",
| 816 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
|
640 { "code": mrc14code,
641 "predicate_test": predicateTest }, [])
| 817 { "code": mrc14code,
818 "predicate_test": predicateTest }, [])
|
642 header_output += RegRegOpDeclare.subst(mrc14Iop)
643 decoder_output += RegRegOpConstructor.subst(mrc14Iop)
| 819 header_output += RegRegImmOpDeclare.subst(mrc14Iop)
820 decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
|
644 exec_output += PredOpExecute.subst(mrc14Iop)
645
646
647 mcr14code = '''
| 821 exec_output += PredOpExecute.subst(mrc14Iop)
822
823
824 mcr14code = '''
|
648 CPSR cpsr = Cpsr;
649 if (cpsr.mode == MODE_USER) {
650 if (FullSystem)
651 return new UndefinedInstruction;
652 else
653 return new UndefinedInstruction(false, mnemonic);
| 825 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
826 if (!canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) {
827 return new UndefinedInstruction(machInst, false, mnemonic);
|
654 }
| 828 }
|
| 829 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
830 Hstr, Hcptr, imm)) {
831 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC);
832 }
|
655 MiscDest = Op1;
656 '''
| 833 MiscDest = Op1;
834 '''
|
657 mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegOp",
| 835 mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
|
658 { "code": mcr14code,
659 "predicate_test": predicateTest },
660 ["IsSerializeAfter","IsNonSpeculative"])
| 836 { "code": mcr14code,
837 "predicate_test": predicateTest },
838 ["IsSerializeAfter","IsNonSpeculative"])
|
661 header_output += RegRegOpDeclare.subst(mcr14Iop)
662 decoder_output += RegRegOpConstructor.subst(mcr14Iop)
| 839 header_output += RegRegImmOpDeclare.subst(mcr14Iop)
840 decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
|
663 exec_output += PredOpExecute.subst(mcr14Iop)
664
| 841 exec_output += PredOpExecute.subst(mcr14Iop)
842
|
665 mrc14UserIop = InstObjParams("mrc", "Mrc14User", "RegRegOp",
666 { "code": "Dest = MiscOp1;",
667 "predicate_test": predicateTest }, [])
668 header_output += RegRegOpDeclare.subst(mrc14UserIop)
669 decoder_output += RegRegOpConstructor.subst(mrc14UserIop)
670 exec_output += PredOpExecute.subst(mrc14UserIop)
671
672 mcr14UserIop = InstObjParams("mcr", "Mcr14User", "RegRegOp",
673 { "code": "MiscDest = Op1",
674 "predicate_test": predicateTest },
675 ["IsSerializeAfter","IsNonSpeculative"])
676 header_output += RegRegOpDeclare.subst(mcr14UserIop)
677 decoder_output += RegRegOpConstructor.subst(mcr14UserIop)
678 exec_output += PredOpExecute.subst(mcr14UserIop)
679
| |
680 mrc15code = '''
| 843 mrc15code = '''
|
681 CPSR cpsr = Cpsr;
682 if (cpsr.mode == MODE_USER) {
683 if (FullSystem)
684 return new UndefinedInstruction;
685 else
686 return new UndefinedInstruction(false, mnemonic);
| 844 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
845 MiscRegIndex miscReg = (MiscRegIndex)
846 xc->tcBase()->flattenMiscIndex(preFlatOp1);
847 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
848 Hcptr, imm);
849 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
850
851 // if we're in non secure PL1 mode then we can trap regargless of whether
852 // the register is accessable, in other modes we trap if only if the register
853 // IS accessable.
854 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
855 return new UndefinedInstruction(machInst, false, mnemonic);
|
687 }
| 856 }
|
688 Dest = MiscOp1;
| 857 if (hypTrap) {
858 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC);
859 }
860 Dest = MiscNsBankedOp1;
|
689 '''
690
| 861 '''
862
|
691 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
| 863 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegImmOp",
|
692 { "code": mrc15code,
693 "predicate_test": predicateTest }, [])
| 864 { "code": mrc15code,
865 "predicate_test": predicateTest }, [])
|
694 header_output += RegRegOpDeclare.subst(mrc15Iop)
695 decoder_output += RegRegOpConstructor.subst(mrc15Iop)
| 866 header_output += RegRegImmOpDeclare.subst(mrc15Iop)
867 decoder_output += RegRegImmOpConstructor.subst(mrc15Iop)
|
696 exec_output += PredOpExecute.subst(mrc15Iop)
697
698
699 mcr15code = '''
| 868 exec_output += PredOpExecute.subst(mrc15Iop)
869
870
871 mcr15code = '''
|
700 CPSR cpsr = Cpsr;
701 if (cpsr.mode == MODE_USER) {
702 if (FullSystem)
703 return new UndefinedInstruction;
704 else
705 return new UndefinedInstruction(false, mnemonic);
| 872 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
873 MiscRegIndex miscReg = (MiscRegIndex)
874 xc->tcBase()->flattenMiscIndex(preFlatDest);
875 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
876 Hcptr, imm);
877 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
878
879 // if we're in non secure PL1 mode then we can trap regargless of whether
880 // the register is accessable, in other modes we trap if only if the register
881 // IS accessable.
882 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
883 return new UndefinedInstruction(machInst, false, mnemonic);
|
706 }
| 884 }
|
707 MiscDest = Op1;
| 885 if (hypTrap) {
886 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC);
887 }
888 MiscNsBankedDest = Op1;
|
708 '''
| 889 '''
|
709 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
| 890 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegImmOp",
|
710 { "code": mcr15code,
711 "predicate_test": predicateTest },
712 ["IsSerializeAfter","IsNonSpeculative"])
| 891 { "code": mcr15code,
892 "predicate_test": predicateTest },
893 ["IsSerializeAfter","IsNonSpeculative"])
|
713 header_output += RegRegOpDeclare.subst(mcr15Iop)
714 decoder_output += RegRegOpConstructor.subst(mcr15Iop)
| 894 header_output += RegRegImmOpDeclare.subst(mcr15Iop)
895 decoder_output += RegRegImmOpConstructor.subst(mcr15Iop)
|
715 exec_output += PredOpExecute.subst(mcr15Iop)
716
| 896 exec_output += PredOpExecute.subst(mcr15Iop)
897
|
717 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
718 { "code": "Dest = MiscOp1;",
719 "predicate_test": predicateTest }, [])
720 header_output += RegRegOpDeclare.subst(mrc15UserIop)
721 decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
722 exec_output += PredOpExecute.subst(mrc15UserIop)
| |
723
| 898
|
724 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
725 { "code": "MiscDest = Op1",
726 "predicate_test": predicateTest },
727 ["IsSerializeAfter","IsNonSpeculative"])
728 header_output += RegRegOpDeclare.subst(mcr15UserIop)
729 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
730 exec_output += PredOpExecute.subst(mcr15UserIop)
| 899 mrrc15code = '''
900 int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
901 MiscRegIndex miscReg = (MiscRegIndex)
902 xc->tcBase()->flattenMiscIndex(preFlatOp1);
903 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
904 bool canRead = canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
|
731
| 905
|
| 906 // if we're in non secure PL1 mode then we can trap regargless of whether
907 // the register is accessable, in other modes we trap if only if the register
908 // IS accessable.
909 if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
910 return new UndefinedInstruction(machInst, false, mnemonic);
911 }
912 if (hypTrap) {
913 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC);
914 }
915 Dest = bits(MiscNsBankedOp164, 63, 32);
916 Dest2 = bits(MiscNsBankedOp164, 31, 0);
917 '''
918 mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
919 { "code": mrrc15code,
920 "predicate_test": predicateTest }, [])
921 header_output += MrrcOpDeclare.subst(mrrc15Iop)
922 decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
923 exec_output += PredOpExecute.subst(mrrc15Iop)
924
925
926 mcrr15code = '''
927 int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
928 MiscRegIndex miscReg = (MiscRegIndex)
929 xc->tcBase()->flattenMiscIndex(preFlatDest);
930 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
931 bool canWrite = canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase());
932
933 // if we're in non secure PL1 mode then we can trap regargless of whether
934 // the register is accessable, in other modes we trap if only if the register
935 // IS accessable.
936 if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) {
937 return new UndefinedInstruction(machInst, false, mnemonic);
938 }
939 if (hypTrap) {
940 return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC);
941 }
942 MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
943 '''
944 mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
945 { "code": mcrr15code,
946 "predicate_test": predicateTest }, [])
947 header_output += McrrOpDeclare.subst(mcrr15Iop)
948 decoder_output += McrrOpConstructor.subst(mcrr15Iop)
949 exec_output += PredOpExecute.subst(mcrr15Iop)
950
951
|
732 enterxCode = '''
733 NextThumb = true;
734 NextJazelle = true;
735 '''
736 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
737 { "code": enterxCode,
738 "predicate_test": predicateTest }, [])
739 header_output += BasicDeclare.subst(enterxIop)
740 decoder_output += BasicConstructor.subst(enterxIop)
741 exec_output += PredOpExecute.subst(enterxIop)
742
743 leavexCode = '''
744 NextThumb = true;
745 NextJazelle = false;
746 '''
747 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
748 { "code": leavexCode,
749 "predicate_test": predicateTest }, [])
750 header_output += BasicDeclare.subst(leavexIop)
751 decoder_output += BasicConstructor.subst(leavexIop)
752 exec_output += PredOpExecute.subst(leavexIop)
753
754 setendCode = '''
755 CPSR cpsr = Cpsr;
756 cpsr.e = imm;
757 Cpsr = cpsr;
758 '''
759 setendIop = InstObjParams("setend", "Setend", "ImmOp",
760 { "code": setendCode,
761 "predicate_test": predicateTest },
762 ["IsSerializeAfter","IsNonSpeculative"])
763 header_output += ImmOpDeclare.subst(setendIop)
764 decoder_output += ImmOpConstructor.subst(setendIop)
765 exec_output += PredOpExecute.subst(setendIop)
766
767 clrexCode = '''
768 LLSCLock = 0;
769 '''
770 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
771 { "code": clrexCode,
772 "predicate_test": predicateTest },[])
773 header_output += BasicDeclare.subst(clrexIop)
774 decoder_output += BasicConstructor.subst(clrexIop)
775 exec_output += PredOpExecute.subst(clrexIop)
776
777 isbCode = '''
| 952 enterxCode = '''
953 NextThumb = true;
954 NextJazelle = true;
955 '''
956 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
957 { "code": enterxCode,
958 "predicate_test": predicateTest }, [])
959 header_output += BasicDeclare.subst(enterxIop)
960 decoder_output += BasicConstructor.subst(enterxIop)
961 exec_output += PredOpExecute.subst(enterxIop)
962
963 leavexCode = '''
964 NextThumb = true;
965 NextJazelle = false;
966 '''
967 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
968 { "code": leavexCode,
969 "predicate_test": predicateTest }, [])
970 header_output += BasicDeclare.subst(leavexIop)
971 decoder_output += BasicConstructor.subst(leavexIop)
972 exec_output += PredOpExecute.subst(leavexIop)
973
974 setendCode = '''
975 CPSR cpsr = Cpsr;
976 cpsr.e = imm;
977 Cpsr = cpsr;
978 '''
979 setendIop = InstObjParams("setend", "Setend", "ImmOp",
980 { "code": setendCode,
981 "predicate_test": predicateTest },
982 ["IsSerializeAfter","IsNonSpeculative"])
983 header_output += ImmOpDeclare.subst(setendIop)
984 decoder_output += ImmOpConstructor.subst(setendIop)
985 exec_output += PredOpExecute.subst(setendIop)
986
987 clrexCode = '''
988 LLSCLock = 0;
989 '''
990 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
991 { "code": clrexCode,
992 "predicate_test": predicateTest },[])
993 header_output += BasicDeclare.subst(clrexIop)
994 decoder_output += BasicConstructor.subst(clrexIop)
995 exec_output += PredOpExecute.subst(clrexIop)
996
997 isbCode = '''
|
| 998 // If the barrier is due to a CP15 access check for hyp traps
999 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
1000 Hdcr, Hstr, Hcptr, imm)) {
1001 return new HypervisorTrap(machInst, imm,
1002 EC_TRAPPED_CP15_MCR_MRC);
1003 }
|
778 fault = new FlushPipe;
779 '''
| 1004 fault = new FlushPipe;
1005 '''
|
780 isbIop = InstObjParams("isb", "Isb", "PredOp",
| 1006 isbIop = InstObjParams("isb", "Isb", "ImmOp",
|
781 {"code": isbCode,
782 "predicate_test": predicateTest},
783 ['IsSerializeAfter'])
| 1007 {"code": isbCode,
1008 "predicate_test": predicateTest},
1009 ['IsSerializeAfter'])
|
784 header_output += BasicDeclare.subst(isbIop)
785 decoder_output += BasicConstructor.subst(isbIop)
| 1010 header_output += ImmOpDeclare.subst(isbIop)
1011 decoder_output += ImmOpConstructor.subst(isbIop)
|
786 exec_output += PredOpExecute.subst(isbIop)
787
788 dsbCode = '''
| 1012 exec_output += PredOpExecute.subst(isbIop)
1013
1014 dsbCode = '''
|
| 1015 // If the barrier is due to a CP15 access check for hyp traps
1016 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr,
1017 Hdcr, Hstr, Hcptr, imm)) {
1018 return new HypervisorTrap(machInst, imm,
1019 EC_TRAPPED_CP15_MCR_MRC);
1020 }
|
789 fault = new FlushPipe;
790 '''
| 1021 fault = new FlushPipe;
1022 '''
|
791 dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
| 1023 dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
|
792 {"code": dsbCode,
793 "predicate_test": predicateTest},
794 ['IsMemBarrier', 'IsSerializeAfter'])
| 1024 {"code": dsbCode,
1025 "predicate_test": predicateTest},
1026 ['IsMemBarrier', 'IsSerializeAfter'])
|
795 header_output += BasicDeclare.subst(dsbIop)
796 decoder_output += BasicConstructor.subst(dsbIop)
| 1027 header_output += ImmOpDeclare.subst(dsbIop)
1028 decoder_output += ImmOpConstructor.subst(dsbIop)
|
797 exec_output += PredOpExecute.subst(dsbIop)
798
799 dmbCode = '''
| 1029 exec_output += PredOpExecute.subst(dsbIop)
1030
1031 dmbCode = '''
|
| 1032 // If the barrier is due to a CP15 access check for hyp traps
1033 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr,
1034 Hdcr, Hstr, Hcptr, imm)) {
1035 return new HypervisorTrap(machInst, imm,
1036 EC_TRAPPED_CP15_MCR_MRC);
1037 }
|
800 '''
| 1038 '''
|
801 dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
| 1039 dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
|
802 {"code": dmbCode,
803 "predicate_test": predicateTest},
804 ['IsMemBarrier'])
| 1040 {"code": dmbCode,
1041 "predicate_test": predicateTest},
1042 ['IsMemBarrier'])
|
805 header_output += BasicDeclare.subst(dmbIop)
806 decoder_output += BasicConstructor.subst(dmbIop)
| 1043 header_output += ImmOpDeclare.subst(dmbIop)
1044 decoder_output += ImmOpConstructor.subst(dmbIop)
|
807 exec_output += PredOpExecute.subst(dmbIop)
808
809 dbgCode = '''
810 '''
811 dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
812 {"code": dbgCode,
813 "predicate_test": predicateTest})
814 header_output += BasicDeclare.subst(dbgIop)
815 decoder_output += BasicConstructor.subst(dbgIop)
816 exec_output += PredOpExecute.subst(dbgIop)
817
818 cpsCode = '''
819 uint32_t mode = bits(imm, 4, 0);
820 uint32_t f = bits(imm, 5);
821 uint32_t i = bits(imm, 6);
822 uint32_t a = bits(imm, 7);
823 bool setMode = bits(imm, 8);
824 bool enable = bits(imm, 9);
825 CPSR cpsr = Cpsr;
826 SCTLR sctlr = Sctlr;
827 if (cpsr.mode != MODE_USER) {
828 if (enable) {
829 if (f) cpsr.f = 0;
830 if (i) cpsr.i = 0;
831 if (a) cpsr.a = 0;
832 } else {
833 if (f && !sctlr.nmfi) cpsr.f = 1;
834 if (i) cpsr.i = 1;
835 if (a) cpsr.a = 1;
836 }
837 if (setMode) {
838 cpsr.mode = mode;
839 }
840 }
841 Cpsr = cpsr;
842 '''
843 cpsIop = InstObjParams("cps", "Cps", "ImmOp",
844 { "code": cpsCode,
845 "predicate_test": predicateTest },
846 ["IsSerializeAfter","IsNonSpeculative"])
847 header_output += ImmOpDeclare.subst(cpsIop)
848 decoder_output += ImmOpConstructor.subst(cpsIop)
849 exec_output += PredOpExecute.subst(cpsIop)
850}};
| 1045 exec_output += PredOpExecute.subst(dmbIop)
1046
1047 dbgCode = '''
1048 '''
1049 dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
1050 {"code": dbgCode,
1051 "predicate_test": predicateTest})
1052 header_output += BasicDeclare.subst(dbgIop)
1053 decoder_output += BasicConstructor.subst(dbgIop)
1054 exec_output += PredOpExecute.subst(dbgIop)
1055
1056 cpsCode = '''
1057 uint32_t mode = bits(imm, 4, 0);
1058 uint32_t f = bits(imm, 5);
1059 uint32_t i = bits(imm, 6);
1060 uint32_t a = bits(imm, 7);
1061 bool setMode = bits(imm, 8);
1062 bool enable = bits(imm, 9);
1063 CPSR cpsr = Cpsr;
1064 SCTLR sctlr = Sctlr;
1065 if (cpsr.mode != MODE_USER) {
1066 if (enable) {
1067 if (f) cpsr.f = 0;
1068 if (i) cpsr.i = 0;
1069 if (a) cpsr.a = 0;
1070 } else {
1071 if (f && !sctlr.nmfi) cpsr.f = 1;
1072 if (i) cpsr.i = 1;
1073 if (a) cpsr.a = 1;
1074 }
1075 if (setMode) {
1076 cpsr.mode = mode;
1077 }
1078 }
1079 Cpsr = cpsr;
1080 '''
1081 cpsIop = InstObjParams("cps", "Cps", "ImmOp",
1082 { "code": cpsCode,
1083 "predicate_test": predicateTest },
1084 ["IsSerializeAfter","IsNonSpeculative"])
1085 header_output += ImmOpDeclare.subst(cpsIop)
1086 decoder_output += ImmOpConstructor.subst(cpsIop)
1087 exec_output += PredOpExecute.subst(cpsIop)
1088}};
|