118 CondCodes = CondCodesMask & newCpsr; 119 ''' 120 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 121 { "code": msrCpsrImmCode, 122 "predicate_test": condPredicateTest }, 123 ["IsSerializeAfter","IsNonSpeculative"]) 124 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 125 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 126 exec_output += PredOpExecute.subst(msrCpsrImmIop) 127 128 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 129 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 130 { "code": msrSpsrImmCode, 131 "predicate_test": predicateTest }, 132 ["IsSerializeAfter","IsNonSpeculative"]) 133 header_output += MsrImmDeclare.subst(msrSpsrImmIop) 134 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 135 exec_output += PredOpExecute.subst(msrSpsrImmIop) 136 137 revCode = ''' 138 uint32_t val = Op1; 139 Dest = swap_byte(val); 140 ''' 141 revIop = InstObjParams("rev", "Rev", "RegRegOp", 142 { "code": revCode, 143 "predicate_test": predicateTest }, []) 144 header_output += RegRegOpDeclare.subst(revIop) 145 decoder_output += RegRegOpConstructor.subst(revIop) 146 exec_output += PredOpExecute.subst(revIop) 147 148 rev16Code = ''' 149 uint32_t val = Op1; 150 Dest = (bits(val, 15, 8) << 0) | 151 (bits(val, 7, 0) << 8) | 152 (bits(val, 31, 24) << 16) | 153 (bits(val, 23, 16) << 24); 154 ''' 155 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 156 { "code": rev16Code, 157 "predicate_test": predicateTest }, []) 158 header_output += RegRegOpDeclare.subst(rev16Iop) 159 decoder_output += RegRegOpConstructor.subst(rev16Iop) 160 exec_output += PredOpExecute.subst(rev16Iop) 161 162 revshCode = ''' 163 uint16_t val = Op1; 164 Dest = sext<16>(swap_byte(val)); 165 ''' 166 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 167 { "code": revshCode, 168 "predicate_test": predicateTest }, []) 169 header_output += RegRegOpDeclare.subst(revshIop) 170 decoder_output += RegRegOpConstructor.subst(revshIop) 171 exec_output += PredOpExecute.subst(revshIop) 172 173 rbitCode = ''' 174 uint8_t *opBytes = (uint8_t *)&Op1; 175 uint32_t resTemp; 176 uint8_t *destBytes = (uint8_t *)&resTemp; 177 // This reverses the bytes and bits of the input, or so says the 178 // internet. 179 for (int i = 0; i < 4; i++) { 180 uint32_t temp = opBytes[i]; 181 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 182 destBytes[3 - i] = (temp * 0x10101) >> 16; 183 } 184 Dest = resTemp; 185 ''' 186 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 187 { "code": rbitCode, 188 "predicate_test": predicateTest }, []) 189 header_output += RegRegOpDeclare.subst(rbitIop) 190 decoder_output += RegRegOpConstructor.subst(rbitIop) 191 exec_output += PredOpExecute.subst(rbitIop) 192 193 clzCode = ''' 194 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 195 ''' 196 clzIop = InstObjParams("clz", "Clz", "RegRegOp", 197 { "code": clzCode, 198 "predicate_test": predicateTest }, []) 199 header_output += RegRegOpDeclare.subst(clzIop) 200 decoder_output += RegRegOpConstructor.subst(clzIop) 201 exec_output += PredOpExecute.subst(clzIop) 202 203 ssatCode = ''' 204 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 205 int32_t res; 206 if (satInt(res, operand, imm)) 207 CondCodes = CondCodes | (1 << 27); 208 else 209 CondCodes = CondCodes; 210 Dest = res; 211 ''' 212 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 213 { "code": ssatCode, 214 "predicate_test": condPredicateTest }, []) 215 header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 216 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 217 exec_output += PredOpExecute.subst(ssatIop) 218 219 usatCode = ''' 220 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 221 int32_t res; 222 if (uSatInt(res, operand, imm)) 223 CondCodes = CondCodes | (1 << 27); 224 else 225 CondCodes = CondCodes; 226 Dest = res; 227 ''' 228 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 229 { "code": usatCode, 230 "predicate_test": condPredicateTest }, []) 231 header_output += RegImmRegShiftOpDeclare.subst(usatIop) 232 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 233 exec_output += PredOpExecute.subst(usatIop) 234 235 ssat16Code = ''' 236 int32_t res; 237 uint32_t resTemp = 0; 238 CondCodes = CondCodes; 239 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 240 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 241 if (satInt(res, argLow, imm)) 242 CondCodes = CondCodes | (1 << 27); 243 replaceBits(resTemp, 15, 0, res); 244 if (satInt(res, argHigh, imm)) 245 CondCodes = CondCodes | (1 << 27); 246 replaceBits(resTemp, 31, 16, res); 247 Dest = resTemp; 248 ''' 249 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 250 { "code": ssat16Code, 251 "predicate_test": condPredicateTest }, []) 252 header_output += RegImmRegOpDeclare.subst(ssat16Iop) 253 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 254 exec_output += PredOpExecute.subst(ssat16Iop) 255 256 usat16Code = ''' 257 int32_t res; 258 uint32_t resTemp = 0; 259 CondCodes = CondCodes; 260 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 261 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 262 if (uSatInt(res, argLow, imm)) 263 CondCodes = CondCodes | (1 << 27); 264 replaceBits(resTemp, 15, 0, res); 265 if (uSatInt(res, argHigh, imm)) 266 CondCodes = CondCodes | (1 << 27); 267 replaceBits(resTemp, 31, 16, res); 268 Dest = resTemp; 269 ''' 270 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 271 { "code": usat16Code, 272 "predicate_test": condPredicateTest }, []) 273 header_output += RegImmRegOpDeclare.subst(usat16Iop) 274 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 275 exec_output += PredOpExecute.subst(usat16Iop) 276 277 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 278 { "code": 279 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 280 "predicate_test": predicateTest }, []) 281 header_output += RegImmRegOpDeclare.subst(sxtbIop) 282 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 283 exec_output += PredOpExecute.subst(sxtbIop) 284 285 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 286 { "code": 287 ''' 288 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 289 Op1; 290 ''', 291 "predicate_test": predicateTest }, []) 292 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 293 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 294 exec_output += PredOpExecute.subst(sxtabIop) 295 296 sxtb16Code = ''' 297 uint32_t resTemp = 0; 298 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 299 replaceBits(resTemp, 31, 16, 300 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 301 Dest = resTemp; 302 ''' 303 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 304 { "code": sxtb16Code, 305 "predicate_test": predicateTest }, []) 306 header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 307 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 308 exec_output += PredOpExecute.subst(sxtb16Iop) 309 310 sxtab16Code = ''' 311 uint32_t resTemp = 0; 312 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 313 bits(Op1, 15, 0)); 314 replaceBits(resTemp, 31, 16, 315 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 316 bits(Op1, 31, 16)); 317 Dest = resTemp; 318 ''' 319 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 320 { "code": sxtab16Code, 321 "predicate_test": predicateTest }, []) 322 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 323 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 324 exec_output += PredOpExecute.subst(sxtab16Iop) 325 326 sxthCode = ''' 327 uint64_t rotated = (uint32_t)Op1; 328 rotated = (rotated | (rotated << 32)) >> imm; 329 Dest = sext<16>((uint16_t)rotated); 330 ''' 331 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 332 { "code": sxthCode, 333 "predicate_test": predicateTest }, []) 334 header_output += RegImmRegOpDeclare.subst(sxthIop) 335 decoder_output += RegImmRegOpConstructor.subst(sxthIop) 336 exec_output += PredOpExecute.subst(sxthIop) 337 338 sxtahCode = ''' 339 uint64_t rotated = (uint32_t)Op2; 340 rotated = (rotated | (rotated << 32)) >> imm; 341 Dest = sext<16>((uint16_t)rotated) + Op1; 342 ''' 343 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 344 { "code": sxtahCode, 345 "predicate_test": predicateTest }, []) 346 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 347 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 348 exec_output += PredOpExecute.subst(sxtahIop) 349 350 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 351 { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 352 "predicate_test": predicateTest }, []) 353 header_output += RegImmRegOpDeclare.subst(uxtbIop) 354 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 355 exec_output += PredOpExecute.subst(uxtbIop) 356 357 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 358 { "code": 359 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 360 "predicate_test": predicateTest }, []) 361 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 362 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 363 exec_output += PredOpExecute.subst(uxtabIop) 364 365 uxtb16Code = ''' 366 uint32_t resTemp = 0; 367 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 368 replaceBits(resTemp, 31, 16, 369 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 370 Dest = resTemp; 371 ''' 372 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 373 { "code": uxtb16Code, 374 "predicate_test": predicateTest }, []) 375 header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 376 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 377 exec_output += PredOpExecute.subst(uxtb16Iop) 378 379 uxtab16Code = ''' 380 uint32_t resTemp = 0; 381 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 382 bits(Op1, 15, 0)); 383 replaceBits(resTemp, 31, 16, 384 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 385 bits(Op1, 31, 16)); 386 Dest = resTemp; 387 ''' 388 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 389 { "code": uxtab16Code, 390 "predicate_test": predicateTest }, []) 391 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 392 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 393 exec_output += PredOpExecute.subst(uxtab16Iop) 394 395 uxthCode = ''' 396 uint64_t rotated = (uint32_t)Op1; 397 rotated = (rotated | (rotated << 32)) >> imm; 398 Dest = (uint16_t)rotated; 399 ''' 400 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 401 { "code": uxthCode, 402 "predicate_test": predicateTest }, []) 403 header_output += RegImmRegOpDeclare.subst(uxthIop) 404 decoder_output += RegImmRegOpConstructor.subst(uxthIop) 405 exec_output += PredOpExecute.subst(uxthIop) 406 407 uxtahCode = ''' 408 uint64_t rotated = (uint32_t)Op2; 409 rotated = (rotated | (rotated << 32)) >> imm; 410 Dest = (uint16_t)rotated + Op1; 411 ''' 412 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 413 { "code": uxtahCode, 414 "predicate_test": predicateTest }, []) 415 header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 416 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 417 exec_output += PredOpExecute.subst(uxtahIop) 418 419 selCode = ''' 420 uint32_t resTemp = 0; 421 for (unsigned i = 0; i < 4; i++) { 422 int low = i * 8; 423 int high = low + 7; 424 replaceBits(resTemp, high, low, 425 bits(CondCodes, 16 + i) ? 426 bits(Op1, high, low) : bits(Op2, high, low)); 427 } 428 Dest = resTemp; 429 ''' 430 selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 431 { "code": selCode, 432 "predicate_test": condPredicateTest }, []) 433 header_output += RegRegRegOpDeclare.subst(selIop) 434 decoder_output += RegRegRegOpConstructor.subst(selIop) 435 exec_output += PredOpExecute.subst(selIop) 436 437 usad8Code = ''' 438 uint32_t resTemp = 0; 439 for (unsigned i = 0; i < 4; i++) { 440 int low = i * 8; 441 int high = low + 7; 442 int32_t diff = bits(Op1, high, low) - 443 bits(Op2, high, low); 444 resTemp += ((diff < 0) ? -diff : diff); 445 } 446 Dest = resTemp; 447 ''' 448 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 449 { "code": usad8Code, 450 "predicate_test": predicateTest }, []) 451 header_output += RegRegRegOpDeclare.subst(usad8Iop) 452 decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 453 exec_output += PredOpExecute.subst(usad8Iop) 454 455 usada8Code = ''' 456 uint32_t resTemp = 0; 457 for (unsigned i = 0; i < 4; i++) { 458 int low = i * 8; 459 int high = low + 7; 460 int32_t diff = bits(Op1, high, low) - 461 bits(Op2, high, low); 462 resTemp += ((diff < 0) ? -diff : diff); 463 } 464 Dest = Op3 + resTemp; 465 ''' 466 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 467 { "code": usada8Code, 468 "predicate_test": predicateTest }, []) 469 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 470 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 471 exec_output += PredOpExecute.subst(usada8Iop) 472 473 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 474 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 475 header_output += BasicDeclare.subst(bkptIop) 476 decoder_output += BasicConstructor.subst(bkptIop) 477 exec_output += BasicExecute.subst(bkptIop) 478 479 nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 480 { "code" : "", "predicate_test" : predicateTest }, 481 ['IsNop']) 482 header_output += BasicDeclare.subst(nopIop) 483 decoder_output += BasicConstructor.subst(nopIop) 484 exec_output += PredOpExecute.subst(nopIop) 485 486 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 487 { "code" : "", "predicate_test" : predicateTest }) 488 header_output += BasicDeclare.subst(yieldIop) 489 decoder_output += BasicConstructor.subst(yieldIop) 490 exec_output += PredOpExecute.subst(yieldIop) 491 492 wfeCode = ''' 493#if FULL_SYSTEM 494 if (SevMailbox) { 495 SevMailbox = 0; 496 PseudoInst::quiesceSkip(xc->tcBase()); 497 } 498 else { 499 PseudoInst::quiesce(xc->tcBase()); 500 } 501#endif 502 ''' 503 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 504 { "code" : wfeCode, "predicate_test" : predicateTest }, 505 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 506 header_output += BasicDeclare.subst(wfeIop) 507 decoder_output += BasicConstructor.subst(wfeIop) 508 exec_output += QuiescePredOpExecute.subst(wfeIop) 509 510 wfiCode = ''' 511#if FULL_SYSTEM 512 PseudoInst::quiesce(xc->tcBase()); 513#endif 514 ''' 515 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 516 { "code" : wfiCode, "predicate_test" : predicateTest }, 517 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 518 header_output += BasicDeclare.subst(wfiIop) 519 decoder_output += BasicConstructor.subst(wfiIop) 520 exec_output += QuiescePredOpExecute.subst(wfiIop) 521 522 sevCode = ''' 523 // Need a way for O3 to not scoreboard these accesses as pipe flushes. 524 SevMailbox = 1; 525 System *sys = xc->tcBase()->getSystemPtr(); 526 for (int x = 0; x < sys->numContexts(); x++) { 527 ThreadContext *oc = sys->getThreadContext(x); 528 if (oc != xc->tcBase()) { 529 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 530 } 531 } 532 ''' 533 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 534 { "code" : sevCode, "predicate_test" : predicateTest }, 535 ["IsNonSpeculative", "IsSquashAfter"]) 536 header_output += BasicDeclare.subst(sevIop) 537 decoder_output += BasicConstructor.subst(sevIop) 538 exec_output += PredOpExecute.subst(sevIop) 539 540 itIop = InstObjParams("it", "ItInst", "PredOp", \
| 110 CondCodes = CondCodesMask & newCpsr; 111 ''' 112 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 113 { "code": msrCpsrImmCode, 114 "predicate_test": condPredicateTest }, 115 ["IsSerializeAfter","IsNonSpeculative"]) 116 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 117 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 118 exec_output += PredOpExecute.subst(msrCpsrImmIop) 119 120 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 121 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 122 { "code": msrSpsrImmCode, 123 "predicate_test": predicateTest }, 124 ["IsSerializeAfter","IsNonSpeculative"]) 125 header_output += MsrImmDeclare.subst(msrSpsrImmIop) 126 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 127 exec_output += PredOpExecute.subst(msrSpsrImmIop) 128 129 revCode = ''' 130 uint32_t val = Op1; 131 Dest = swap_byte(val); 132 ''' 133 revIop = InstObjParams("rev", "Rev", "RegRegOp", 134 { "code": revCode, 135 "predicate_test": predicateTest }, []) 136 header_output += RegRegOpDeclare.subst(revIop) 137 decoder_output += RegRegOpConstructor.subst(revIop) 138 exec_output += PredOpExecute.subst(revIop) 139 140 rev16Code = ''' 141 uint32_t val = Op1; 142 Dest = (bits(val, 15, 8) << 0) | 143 (bits(val, 7, 0) << 8) | 144 (bits(val, 31, 24) << 16) | 145 (bits(val, 23, 16) << 24); 146 ''' 147 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 148 { "code": rev16Code, 149 "predicate_test": predicateTest }, []) 150 header_output += RegRegOpDeclare.subst(rev16Iop) 151 decoder_output += RegRegOpConstructor.subst(rev16Iop) 152 exec_output += PredOpExecute.subst(rev16Iop) 153 154 revshCode = ''' 155 uint16_t val = Op1; 156 Dest = sext<16>(swap_byte(val)); 157 ''' 158 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 159 { "code": revshCode, 160 "predicate_test": predicateTest }, []) 161 header_output += RegRegOpDeclare.subst(revshIop) 162 decoder_output += RegRegOpConstructor.subst(revshIop) 163 exec_output += PredOpExecute.subst(revshIop) 164 165 rbitCode = ''' 166 uint8_t *opBytes = (uint8_t *)&Op1; 167 uint32_t resTemp; 168 uint8_t *destBytes = (uint8_t *)&resTemp; 169 // This reverses the bytes and bits of the input, or so says the 170 // internet. 171 for (int i = 0; i < 4; i++) { 172 uint32_t temp = opBytes[i]; 173 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 174 destBytes[3 - i] = (temp * 0x10101) >> 16; 175 } 176 Dest = resTemp; 177 ''' 178 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 179 { "code": rbitCode, 180 "predicate_test": predicateTest }, []) 181 header_output += RegRegOpDeclare.subst(rbitIop) 182 decoder_output += RegRegOpConstructor.subst(rbitIop) 183 exec_output += PredOpExecute.subst(rbitIop) 184 185 clzCode = ''' 186 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 187 ''' 188 clzIop = InstObjParams("clz", "Clz", "RegRegOp", 189 { "code": clzCode, 190 "predicate_test": predicateTest }, []) 191 header_output += RegRegOpDeclare.subst(clzIop) 192 decoder_output += RegRegOpConstructor.subst(clzIop) 193 exec_output += PredOpExecute.subst(clzIop) 194 195 ssatCode = ''' 196 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 197 int32_t res; 198 if (satInt(res, operand, imm)) 199 CondCodes = CondCodes | (1 << 27); 200 else 201 CondCodes = CondCodes; 202 Dest = res; 203 ''' 204 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 205 { "code": ssatCode, 206 "predicate_test": condPredicateTest }, []) 207 header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 208 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 209 exec_output += PredOpExecute.subst(ssatIop) 210 211 usatCode = ''' 212 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 213 int32_t res; 214 if (uSatInt(res, operand, imm)) 215 CondCodes = CondCodes | (1 << 27); 216 else 217 CondCodes = CondCodes; 218 Dest = res; 219 ''' 220 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 221 { "code": usatCode, 222 "predicate_test": condPredicateTest }, []) 223 header_output += RegImmRegShiftOpDeclare.subst(usatIop) 224 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 225 exec_output += PredOpExecute.subst(usatIop) 226 227 ssat16Code = ''' 228 int32_t res; 229 uint32_t resTemp = 0; 230 CondCodes = CondCodes; 231 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 232 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 233 if (satInt(res, argLow, imm)) 234 CondCodes = CondCodes | (1 << 27); 235 replaceBits(resTemp, 15, 0, res); 236 if (satInt(res, argHigh, imm)) 237 CondCodes = CondCodes | (1 << 27); 238 replaceBits(resTemp, 31, 16, res); 239 Dest = resTemp; 240 ''' 241 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 242 { "code": ssat16Code, 243 "predicate_test": condPredicateTest }, []) 244 header_output += RegImmRegOpDeclare.subst(ssat16Iop) 245 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 246 exec_output += PredOpExecute.subst(ssat16Iop) 247 248 usat16Code = ''' 249 int32_t res; 250 uint32_t resTemp = 0; 251 CondCodes = CondCodes; 252 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 253 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 254 if (uSatInt(res, argLow, imm)) 255 CondCodes = CondCodes | (1 << 27); 256 replaceBits(resTemp, 15, 0, res); 257 if (uSatInt(res, argHigh, imm)) 258 CondCodes = CondCodes | (1 << 27); 259 replaceBits(resTemp, 31, 16, res); 260 Dest = resTemp; 261 ''' 262 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 263 { "code": usat16Code, 264 "predicate_test": condPredicateTest }, []) 265 header_output += RegImmRegOpDeclare.subst(usat16Iop) 266 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 267 exec_output += PredOpExecute.subst(usat16Iop) 268 269 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 270 { "code": 271 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 272 "predicate_test": predicateTest }, []) 273 header_output += RegImmRegOpDeclare.subst(sxtbIop) 274 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 275 exec_output += PredOpExecute.subst(sxtbIop) 276 277 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 278 { "code": 279 ''' 280 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 281 Op1; 282 ''', 283 "predicate_test": predicateTest }, []) 284 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 285 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 286 exec_output += PredOpExecute.subst(sxtabIop) 287 288 sxtb16Code = ''' 289 uint32_t resTemp = 0; 290 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 291 replaceBits(resTemp, 31, 16, 292 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 293 Dest = resTemp; 294 ''' 295 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 296 { "code": sxtb16Code, 297 "predicate_test": predicateTest }, []) 298 header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 299 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 300 exec_output += PredOpExecute.subst(sxtb16Iop) 301 302 sxtab16Code = ''' 303 uint32_t resTemp = 0; 304 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 305 bits(Op1, 15, 0)); 306 replaceBits(resTemp, 31, 16, 307 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 308 bits(Op1, 31, 16)); 309 Dest = resTemp; 310 ''' 311 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 312 { "code": sxtab16Code, 313 "predicate_test": predicateTest }, []) 314 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 315 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 316 exec_output += PredOpExecute.subst(sxtab16Iop) 317 318 sxthCode = ''' 319 uint64_t rotated = (uint32_t)Op1; 320 rotated = (rotated | (rotated << 32)) >> imm; 321 Dest = sext<16>((uint16_t)rotated); 322 ''' 323 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 324 { "code": sxthCode, 325 "predicate_test": predicateTest }, []) 326 header_output += RegImmRegOpDeclare.subst(sxthIop) 327 decoder_output += RegImmRegOpConstructor.subst(sxthIop) 328 exec_output += PredOpExecute.subst(sxthIop) 329 330 sxtahCode = ''' 331 uint64_t rotated = (uint32_t)Op2; 332 rotated = (rotated | (rotated << 32)) >> imm; 333 Dest = sext<16>((uint16_t)rotated) + Op1; 334 ''' 335 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 336 { "code": sxtahCode, 337 "predicate_test": predicateTest }, []) 338 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 339 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 340 exec_output += PredOpExecute.subst(sxtahIop) 341 342 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 343 { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 344 "predicate_test": predicateTest }, []) 345 header_output += RegImmRegOpDeclare.subst(uxtbIop) 346 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 347 exec_output += PredOpExecute.subst(uxtbIop) 348 349 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 350 { "code": 351 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 352 "predicate_test": predicateTest }, []) 353 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 354 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 355 exec_output += PredOpExecute.subst(uxtabIop) 356 357 uxtb16Code = ''' 358 uint32_t resTemp = 0; 359 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 360 replaceBits(resTemp, 31, 16, 361 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 362 Dest = resTemp; 363 ''' 364 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 365 { "code": uxtb16Code, 366 "predicate_test": predicateTest }, []) 367 header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 368 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 369 exec_output += PredOpExecute.subst(uxtb16Iop) 370 371 uxtab16Code = ''' 372 uint32_t resTemp = 0; 373 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 374 bits(Op1, 15, 0)); 375 replaceBits(resTemp, 31, 16, 376 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 377 bits(Op1, 31, 16)); 378 Dest = resTemp; 379 ''' 380 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 381 { "code": uxtab16Code, 382 "predicate_test": predicateTest }, []) 383 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 384 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 385 exec_output += PredOpExecute.subst(uxtab16Iop) 386 387 uxthCode = ''' 388 uint64_t rotated = (uint32_t)Op1; 389 rotated = (rotated | (rotated << 32)) >> imm; 390 Dest = (uint16_t)rotated; 391 ''' 392 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 393 { "code": uxthCode, 394 "predicate_test": predicateTest }, []) 395 header_output += RegImmRegOpDeclare.subst(uxthIop) 396 decoder_output += RegImmRegOpConstructor.subst(uxthIop) 397 exec_output += PredOpExecute.subst(uxthIop) 398 399 uxtahCode = ''' 400 uint64_t rotated = (uint32_t)Op2; 401 rotated = (rotated | (rotated << 32)) >> imm; 402 Dest = (uint16_t)rotated + Op1; 403 ''' 404 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 405 { "code": uxtahCode, 406 "predicate_test": predicateTest }, []) 407 header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 408 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 409 exec_output += PredOpExecute.subst(uxtahIop) 410 411 selCode = ''' 412 uint32_t resTemp = 0; 413 for (unsigned i = 0; i < 4; i++) { 414 int low = i * 8; 415 int high = low + 7; 416 replaceBits(resTemp, high, low, 417 bits(CondCodes, 16 + i) ? 418 bits(Op1, high, low) : bits(Op2, high, low)); 419 } 420 Dest = resTemp; 421 ''' 422 selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 423 { "code": selCode, 424 "predicate_test": condPredicateTest }, []) 425 header_output += RegRegRegOpDeclare.subst(selIop) 426 decoder_output += RegRegRegOpConstructor.subst(selIop) 427 exec_output += PredOpExecute.subst(selIop) 428 429 usad8Code = ''' 430 uint32_t resTemp = 0; 431 for (unsigned i = 0; i < 4; i++) { 432 int low = i * 8; 433 int high = low + 7; 434 int32_t diff = bits(Op1, high, low) - 435 bits(Op2, high, low); 436 resTemp += ((diff < 0) ? -diff : diff); 437 } 438 Dest = resTemp; 439 ''' 440 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 441 { "code": usad8Code, 442 "predicate_test": predicateTest }, []) 443 header_output += RegRegRegOpDeclare.subst(usad8Iop) 444 decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 445 exec_output += PredOpExecute.subst(usad8Iop) 446 447 usada8Code = ''' 448 uint32_t resTemp = 0; 449 for (unsigned i = 0; i < 4; i++) { 450 int low = i * 8; 451 int high = low + 7; 452 int32_t diff = bits(Op1, high, low) - 453 bits(Op2, high, low); 454 resTemp += ((diff < 0) ? -diff : diff); 455 } 456 Dest = Op3 + resTemp; 457 ''' 458 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 459 { "code": usada8Code, 460 "predicate_test": predicateTest }, []) 461 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 462 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 463 exec_output += PredOpExecute.subst(usada8Iop) 464 465 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 466 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 467 header_output += BasicDeclare.subst(bkptIop) 468 decoder_output += BasicConstructor.subst(bkptIop) 469 exec_output += BasicExecute.subst(bkptIop) 470 471 nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 472 { "code" : "", "predicate_test" : predicateTest }, 473 ['IsNop']) 474 header_output += BasicDeclare.subst(nopIop) 475 decoder_output += BasicConstructor.subst(nopIop) 476 exec_output += PredOpExecute.subst(nopIop) 477 478 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 479 { "code" : "", "predicate_test" : predicateTest }) 480 header_output += BasicDeclare.subst(yieldIop) 481 decoder_output += BasicConstructor.subst(yieldIop) 482 exec_output += PredOpExecute.subst(yieldIop) 483 484 wfeCode = ''' 485#if FULL_SYSTEM 486 if (SevMailbox) { 487 SevMailbox = 0; 488 PseudoInst::quiesceSkip(xc->tcBase()); 489 } 490 else { 491 PseudoInst::quiesce(xc->tcBase()); 492 } 493#endif 494 ''' 495 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 496 { "code" : wfeCode, "predicate_test" : predicateTest }, 497 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 498 header_output += BasicDeclare.subst(wfeIop) 499 decoder_output += BasicConstructor.subst(wfeIop) 500 exec_output += QuiescePredOpExecute.subst(wfeIop) 501 502 wfiCode = ''' 503#if FULL_SYSTEM 504 PseudoInst::quiesce(xc->tcBase()); 505#endif 506 ''' 507 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 508 { "code" : wfiCode, "predicate_test" : predicateTest }, 509 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 510 header_output += BasicDeclare.subst(wfiIop) 511 decoder_output += BasicConstructor.subst(wfiIop) 512 exec_output += QuiescePredOpExecute.subst(wfiIop) 513 514 sevCode = ''' 515 // Need a way for O3 to not scoreboard these accesses as pipe flushes. 516 SevMailbox = 1; 517 System *sys = xc->tcBase()->getSystemPtr(); 518 for (int x = 0; x < sys->numContexts(); x++) { 519 ThreadContext *oc = sys->getThreadContext(x); 520 if (oc != xc->tcBase()) { 521 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 522 } 523 } 524 ''' 525 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 526 { "code" : sevCode, "predicate_test" : predicateTest }, 527 ["IsNonSpeculative", "IsSquashAfter"]) 528 header_output += BasicDeclare.subst(sevIop) 529 decoder_output += BasicConstructor.subst(sevIop) 530 exec_output += PredOpExecute.subst(sevIop) 531 532 itIop = InstObjParams("it", "ItInst", "PredOp", \
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542 "predicate_test" : predicateTest }, 543 ["IsNonSpeculative", "IsSerializeAfter"]) 544 header_output += BasicDeclare.subst(itIop) 545 decoder_output += BasicConstructor.subst(itIop) 546 exec_output += PredOpExecute.subst(itIop) 547 unknownCode = ''' 548#if FULL_SYSTEM 549 return new UndefinedInstruction; 550#else 551 return new UndefinedInstruction(machInst, true); 552#endif 553 ''' 554 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 555 { "code": unknownCode, 556 "predicate_test": predicateTest }) 557 header_output += BasicDeclare.subst(unknownIop) 558 decoder_output += BasicConstructor.subst(unknownIop) 559 exec_output += PredOpExecute.subst(unknownIop) 560 561 ubfxCode = ''' 562 Dest = bits(Op1, imm2, imm1); 563 ''' 564 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 565 { "code": ubfxCode, 566 "predicate_test": predicateTest }, []) 567 header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 568 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 569 exec_output += PredOpExecute.subst(ubfxIop) 570 571 sbfxCode = ''' 572 int32_t resTemp = bits(Op1, imm2, imm1); 573 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 574 ''' 575 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 576 { "code": sbfxCode, 577 "predicate_test": predicateTest }, []) 578 header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 579 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 580 exec_output += PredOpExecute.subst(sbfxIop) 581 582 bfcCode = ''' 583 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 584 ''' 585 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 586 { "code": bfcCode, 587 "predicate_test": predicateTest }, []) 588 header_output += RegRegImmImmOpDeclare.subst(bfcIop) 589 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 590 exec_output += PredOpExecute.subst(bfcIop) 591 592 bfiCode = ''' 593 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 594 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 595 ''' 596 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 597 { "code": bfiCode, 598 "predicate_test": predicateTest }, []) 599 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 600 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 601 exec_output += PredOpExecute.subst(bfiIop) 602 603 mrc15code = ''' 604 CPSR cpsr = Cpsr; 605 if (cpsr.mode == MODE_USER) 606#if FULL_SYSTEM 607 return new UndefinedInstruction; 608#else 609 return new UndefinedInstruction(false, mnemonic); 610#endif 611 Dest = MiscOp1; 612 ''' 613 614 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 615 { "code": mrc15code, 616 "predicate_test": predicateTest }, []) 617 header_output += RegRegOpDeclare.subst(mrc15Iop) 618 decoder_output += RegRegOpConstructor.subst(mrc15Iop) 619 exec_output += PredOpExecute.subst(mrc15Iop) 620 621 622 mcr15code = ''' 623 CPSR cpsr = Cpsr; 624 if (cpsr.mode == MODE_USER) 625#if FULL_SYSTEM 626 return new UndefinedInstruction; 627#else 628 return new UndefinedInstruction(false, mnemonic); 629#endif 630 MiscDest = Op1; 631 ''' 632 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 633 { "code": mcr15code, 634 "predicate_test": predicateTest }, 635 ["IsSerializeAfter","IsNonSpeculative"]) 636 header_output += RegRegOpDeclare.subst(mcr15Iop) 637 decoder_output += RegRegOpConstructor.subst(mcr15Iop) 638 exec_output += PredOpExecute.subst(mcr15Iop) 639 640 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 641 { "code": "Dest = MiscOp1;", 642 "predicate_test": predicateTest }, []) 643 header_output += RegRegOpDeclare.subst(mrc15UserIop) 644 decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 645 exec_output += PredOpExecute.subst(mrc15UserIop) 646 647 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 648 { "code": "MiscDest = Op1", 649 "predicate_test": predicateTest }, 650 ["IsSerializeAfter","IsNonSpeculative"]) 651 header_output += RegRegOpDeclare.subst(mcr15UserIop) 652 decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 653 exec_output += PredOpExecute.subst(mcr15UserIop) 654 655 enterxCode = ''' 656 NextThumb = true; 657 NextJazelle = true; 658 ''' 659 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 660 { "code": enterxCode, 661 "predicate_test": predicateTest }, []) 662 header_output += BasicDeclare.subst(enterxIop) 663 decoder_output += BasicConstructor.subst(enterxIop) 664 exec_output += PredOpExecute.subst(enterxIop) 665 666 leavexCode = ''' 667 NextThumb = true; 668 NextJazelle = false; 669 ''' 670 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 671 { "code": leavexCode, 672 "predicate_test": predicateTest }, []) 673 header_output += BasicDeclare.subst(leavexIop) 674 decoder_output += BasicConstructor.subst(leavexIop) 675 exec_output += PredOpExecute.subst(leavexIop) 676 677 setendCode = ''' 678 CPSR cpsr = Cpsr; 679 cpsr.e = imm; 680 Cpsr = cpsr; 681 ''' 682 setendIop = InstObjParams("setend", "Setend", "ImmOp", 683 { "code": setendCode, 684 "predicate_test": predicateTest }, 685 ["IsSerializeAfter","IsNonSpeculative"]) 686 header_output += ImmOpDeclare.subst(setendIop) 687 decoder_output += ImmOpConstructor.subst(setendIop) 688 exec_output += PredOpExecute.subst(setendIop) 689 690 clrexCode = ''' 691 unsigned memAccessFlags = Request::CLEAR_LL | 692 ArmISA::TLB::AlignWord | Request::LLSC; 693 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); 694 ''' 695 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 696 { "code": clrexCode, 697 "predicate_test": predicateTest },[]) 698 header_output += ClrexDeclare.subst(clrexIop) 699 decoder_output += BasicConstructor.subst(clrexIop) 700 exec_output += PredOpExecute.subst(clrexIop) 701 exec_output += ClrexInitiateAcc.subst(clrexIop) 702 exec_output += ClrexCompleteAcc.subst(clrexIop) 703 704 isbCode = ''' 705 fault = new FlushPipe; 706 ''' 707 isbIop = InstObjParams("isb", "Isb", "PredOp", 708 {"code": isbCode, 709 "predicate_test": predicateTest}, 710 ['IsSerializeAfter']) 711 header_output += BasicDeclare.subst(isbIop) 712 decoder_output += BasicConstructor.subst(isbIop) 713 exec_output += PredOpExecute.subst(isbIop) 714 715 dsbCode = ''' 716 fault = new FlushPipe; 717 ''' 718 dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 719 {"code": dsbCode, 720 "predicate_test": predicateTest}, 721 ['IsMemBarrier', 'IsSerializeAfter']) 722 header_output += BasicDeclare.subst(dsbIop) 723 decoder_output += BasicConstructor.subst(dsbIop) 724 exec_output += PredOpExecute.subst(dsbIop) 725 726 dmbCode = ''' 727 ''' 728 dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 729 {"code": dmbCode, 730 "predicate_test": predicateTest}, 731 ['IsMemBarrier']) 732 header_output += BasicDeclare.subst(dmbIop) 733 decoder_output += BasicConstructor.subst(dmbIop) 734 exec_output += PredOpExecute.subst(dmbIop) 735 736 dbgCode = ''' 737 ''' 738 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 739 {"code": dbgCode, 740 "predicate_test": predicateTest}) 741 header_output += BasicDeclare.subst(dbgIop) 742 decoder_output += BasicConstructor.subst(dbgIop) 743 exec_output += PredOpExecute.subst(dbgIop) 744 745 cpsCode = ''' 746 uint32_t mode = bits(imm, 4, 0); 747 uint32_t f = bits(imm, 5); 748 uint32_t i = bits(imm, 6); 749 uint32_t a = bits(imm, 7); 750 bool setMode = bits(imm, 8); 751 bool enable = bits(imm, 9); 752 CPSR cpsr = Cpsr; 753 SCTLR sctlr = Sctlr; 754 if (cpsr.mode != MODE_USER) { 755 if (enable) { 756 if (f) cpsr.f = 0; 757 if (i) cpsr.i = 0; 758 if (a) cpsr.a = 0; 759 } else { 760 if (f && !sctlr.nmfi) cpsr.f = 1; 761 if (i) cpsr.i = 1; 762 if (a) cpsr.a = 1; 763 } 764 if (setMode) { 765 cpsr.mode = mode; 766 } 767 } 768 Cpsr = cpsr; 769 ''' 770 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 771 { "code": cpsCode, 772 "predicate_test": predicateTest }, 773 ["IsSerializeAfter","IsNonSpeculative"]) 774 header_output += ImmOpDeclare.subst(cpsIop) 775 decoder_output += ImmOpConstructor.subst(cpsIop) 776 exec_output += PredOpExecute.subst(cpsIop) 777}};
| 534 "predicate_test" : predicateTest }, 535 ["IsNonSpeculative", "IsSerializeAfter"]) 536 header_output += BasicDeclare.subst(itIop) 537 decoder_output += BasicConstructor.subst(itIop) 538 exec_output += PredOpExecute.subst(itIop) 539 unknownCode = ''' 540#if FULL_SYSTEM 541 return new UndefinedInstruction; 542#else 543 return new UndefinedInstruction(machInst, true); 544#endif 545 ''' 546 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 547 { "code": unknownCode, 548 "predicate_test": predicateTest }) 549 header_output += BasicDeclare.subst(unknownIop) 550 decoder_output += BasicConstructor.subst(unknownIop) 551 exec_output += PredOpExecute.subst(unknownIop) 552 553 ubfxCode = ''' 554 Dest = bits(Op1, imm2, imm1); 555 ''' 556 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 557 { "code": ubfxCode, 558 "predicate_test": predicateTest }, []) 559 header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 560 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 561 exec_output += PredOpExecute.subst(ubfxIop) 562 563 sbfxCode = ''' 564 int32_t resTemp = bits(Op1, imm2, imm1); 565 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 566 ''' 567 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 568 { "code": sbfxCode, 569 "predicate_test": predicateTest }, []) 570 header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 571 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 572 exec_output += PredOpExecute.subst(sbfxIop) 573 574 bfcCode = ''' 575 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 576 ''' 577 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 578 { "code": bfcCode, 579 "predicate_test": predicateTest }, []) 580 header_output += RegRegImmImmOpDeclare.subst(bfcIop) 581 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 582 exec_output += PredOpExecute.subst(bfcIop) 583 584 bfiCode = ''' 585 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 586 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 587 ''' 588 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 589 { "code": bfiCode, 590 "predicate_test": predicateTest }, []) 591 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 592 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 593 exec_output += PredOpExecute.subst(bfiIop) 594 595 mrc15code = ''' 596 CPSR cpsr = Cpsr; 597 if (cpsr.mode == MODE_USER) 598#if FULL_SYSTEM 599 return new UndefinedInstruction; 600#else 601 return new UndefinedInstruction(false, mnemonic); 602#endif 603 Dest = MiscOp1; 604 ''' 605 606 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 607 { "code": mrc15code, 608 "predicate_test": predicateTest }, []) 609 header_output += RegRegOpDeclare.subst(mrc15Iop) 610 decoder_output += RegRegOpConstructor.subst(mrc15Iop) 611 exec_output += PredOpExecute.subst(mrc15Iop) 612 613 614 mcr15code = ''' 615 CPSR cpsr = Cpsr; 616 if (cpsr.mode == MODE_USER) 617#if FULL_SYSTEM 618 return new UndefinedInstruction; 619#else 620 return new UndefinedInstruction(false, mnemonic); 621#endif 622 MiscDest = Op1; 623 ''' 624 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 625 { "code": mcr15code, 626 "predicate_test": predicateTest }, 627 ["IsSerializeAfter","IsNonSpeculative"]) 628 header_output += RegRegOpDeclare.subst(mcr15Iop) 629 decoder_output += RegRegOpConstructor.subst(mcr15Iop) 630 exec_output += PredOpExecute.subst(mcr15Iop) 631 632 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 633 { "code": "Dest = MiscOp1;", 634 "predicate_test": predicateTest }, []) 635 header_output += RegRegOpDeclare.subst(mrc15UserIop) 636 decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 637 exec_output += PredOpExecute.subst(mrc15UserIop) 638 639 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 640 { "code": "MiscDest = Op1", 641 "predicate_test": predicateTest }, 642 ["IsSerializeAfter","IsNonSpeculative"]) 643 header_output += RegRegOpDeclare.subst(mcr15UserIop) 644 decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 645 exec_output += PredOpExecute.subst(mcr15UserIop) 646 647 enterxCode = ''' 648 NextThumb = true; 649 NextJazelle = true; 650 ''' 651 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 652 { "code": enterxCode, 653 "predicate_test": predicateTest }, []) 654 header_output += BasicDeclare.subst(enterxIop) 655 decoder_output += BasicConstructor.subst(enterxIop) 656 exec_output += PredOpExecute.subst(enterxIop) 657 658 leavexCode = ''' 659 NextThumb = true; 660 NextJazelle = false; 661 ''' 662 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 663 { "code": leavexCode, 664 "predicate_test": predicateTest }, []) 665 header_output += BasicDeclare.subst(leavexIop) 666 decoder_output += BasicConstructor.subst(leavexIop) 667 exec_output += PredOpExecute.subst(leavexIop) 668 669 setendCode = ''' 670 CPSR cpsr = Cpsr; 671 cpsr.e = imm; 672 Cpsr = cpsr; 673 ''' 674 setendIop = InstObjParams("setend", "Setend", "ImmOp", 675 { "code": setendCode, 676 "predicate_test": predicateTest }, 677 ["IsSerializeAfter","IsNonSpeculative"]) 678 header_output += ImmOpDeclare.subst(setendIop) 679 decoder_output += ImmOpConstructor.subst(setendIop) 680 exec_output += PredOpExecute.subst(setendIop) 681 682 clrexCode = ''' 683 unsigned memAccessFlags = Request::CLEAR_LL | 684 ArmISA::TLB::AlignWord | Request::LLSC; 685 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); 686 ''' 687 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 688 { "code": clrexCode, 689 "predicate_test": predicateTest },[]) 690 header_output += ClrexDeclare.subst(clrexIop) 691 decoder_output += BasicConstructor.subst(clrexIop) 692 exec_output += PredOpExecute.subst(clrexIop) 693 exec_output += ClrexInitiateAcc.subst(clrexIop) 694 exec_output += ClrexCompleteAcc.subst(clrexIop) 695 696 isbCode = ''' 697 fault = new FlushPipe; 698 ''' 699 isbIop = InstObjParams("isb", "Isb", "PredOp", 700 {"code": isbCode, 701 "predicate_test": predicateTest}, 702 ['IsSerializeAfter']) 703 header_output += BasicDeclare.subst(isbIop) 704 decoder_output += BasicConstructor.subst(isbIop) 705 exec_output += PredOpExecute.subst(isbIop) 706 707 dsbCode = ''' 708 fault = new FlushPipe; 709 ''' 710 dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 711 {"code": dsbCode, 712 "predicate_test": predicateTest}, 713 ['IsMemBarrier', 'IsSerializeAfter']) 714 header_output += BasicDeclare.subst(dsbIop) 715 decoder_output += BasicConstructor.subst(dsbIop) 716 exec_output += PredOpExecute.subst(dsbIop) 717 718 dmbCode = ''' 719 ''' 720 dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 721 {"code": dmbCode, 722 "predicate_test": predicateTest}, 723 ['IsMemBarrier']) 724 header_output += BasicDeclare.subst(dmbIop) 725 decoder_output += BasicConstructor.subst(dmbIop) 726 exec_output += PredOpExecute.subst(dmbIop) 727 728 dbgCode = ''' 729 ''' 730 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 731 {"code": dbgCode, 732 "predicate_test": predicateTest}) 733 header_output += BasicDeclare.subst(dbgIop) 734 decoder_output += BasicConstructor.subst(dbgIop) 735 exec_output += PredOpExecute.subst(dbgIop) 736 737 cpsCode = ''' 738 uint32_t mode = bits(imm, 4, 0); 739 uint32_t f = bits(imm, 5); 740 uint32_t i = bits(imm, 6); 741 uint32_t a = bits(imm, 7); 742 bool setMode = bits(imm, 8); 743 bool enable = bits(imm, 9); 744 CPSR cpsr = Cpsr; 745 SCTLR sctlr = Sctlr; 746 if (cpsr.mode != MODE_USER) { 747 if (enable) { 748 if (f) cpsr.f = 0; 749 if (i) cpsr.i = 0; 750 if (a) cpsr.a = 0; 751 } else { 752 if (f && !sctlr.nmfi) cpsr.f = 1; 753 if (i) cpsr.i = 1; 754 if (a) cpsr.a = 1; 755 } 756 if (setMode) { 757 cpsr.mode = mode; 758 } 759 } 760 Cpsr = cpsr; 761 ''' 762 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 763 { "code": cpsCode, 764 "predicate_test": predicateTest }, 765 ["IsSerializeAfter","IsNonSpeculative"]) 766 header_output += ImmOpDeclare.subst(cpsIop) 767 decoder_output += ImmOpConstructor.subst(cpsIop) 768 exec_output += PredOpExecute.subst(cpsIop) 769}};
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