1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
43 ThreadContext *tc = xc->tcBase();
44
45 const auto semihost_imm = Thumb? 0xAB : 0x123456;
46
47 if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
48 R0 = ArmSystem::callSemihosting32(tc, R0, R1);
49 } else {
50 fault = std::make_shared<SupervisorCall>(machInst, imm);
51 }
52 '''
53
54 svcIop = InstObjParams("svc", "Svc", "ImmOp",
55 { "code": svcCode,
56 "predicate_test": predicateTest,
57 "thumb_semihost": '0xAB',
58 "arm_semihost": '0x123456' },
59 ["IsSyscall", "IsNonSpeculative",
60 "IsSerializeAfter"])
61 header_output = ImmOpDeclare.subst(svcIop)
62 decoder_output = SemihostConstructor.subst(svcIop)
63 exec_output = PredOpExecute.subst(svcIop)
64
65 hltCode = '''
66 ThreadContext *tc = xc->tcBase();
67
68 const auto semihost_imm = Thumb? 0x3C : 0xF000;
69
70 if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
71 R0 = ArmSystem::callSemihosting32(tc, R0, R1);
72 } else {
73 // HLT instructions aren't implemented, so treat them as undefined
74 // instructions.
75 fault = std::make_shared<UndefinedInstruction>(
76 machInst, false, mnemonic);
77 }
78 '''
79
80 hltIop = InstObjParams("hlt", "Hlt", "ImmOp",
81 { "code": hltCode,
82 "predicate_test": predicateTest,
83 "thumb_semihost": '0x3C',
84 "arm_semihost": '0xF000' },
85 ["IsNonSpeculative"])
86 header_output += ImmOpDeclare.subst(hltIop)
87 decoder_output += SemihostConstructor.subst(hltIop)
88 exec_output += PredOpExecute.subst(hltIop)
89
90 smcCode = '''
91 HCR hcr = Hcr;
92 CPSR cpsr = Cpsr;
93 SCR scr = Scr;
94
95 if ((cpsr.mode != MODE_USER) && FullSystem) {
96 if (ArmSystem::haveVirtualization(xc->tcBase()) &&
97 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
98 fault = std::make_shared<HypervisorTrap>(machInst, 0,
99 EC_SMC_TO_HYP);
100 } else {
101 if (scr.scd) {
102 fault = disabledFault();
103 } else {
104 fault = std::make_shared<SecureMonitorCall>(machInst);
105 }
106 }
107 } else {
108 fault = disabledFault();
109 }
110 '''
111
112 smcIop = InstObjParams("smc", "Smc", "PredOp",
113 { "code": smcCode,
114 "predicate_test": predicateTest },
115 ["IsNonSpeculative", "IsSerializeAfter"])
116 header_output += BasicDeclare.subst(smcIop)
117 decoder_output += BasicConstructor.subst(smcIop)
118 exec_output += PredOpExecute.subst(smcIop)
119
120 hvcCode = '''
121 CPSR cpsr = Cpsr;
122 SCR scr = Scr;
123
124 // Filter out the various cases where this instruction isn't defined
125 if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
126 (cpsr.mode == MODE_USER) ||
127 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
128 fault = disabledFault();
129 } else {
130 fault = std::make_shared<HypervisorCall>(machInst, imm);
131 }
132 '''
133
134 hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
135 { "code": hvcCode,
136 "predicate_test": predicateTest },
137 ["IsNonSpeculative", "IsSerializeAfter"])
138 header_output += ImmOpDeclare.subst(hvcIop)
139 decoder_output += ImmOpConstructor.subst(hvcIop)
140 exec_output += PredOpExecute.subst(hvcIop)
141
142 eretCode = '''
143 SCTLR sctlr = Sctlr;
144 CPSR old_cpsr = Cpsr;
145 old_cpsr.nz = CondCodesNZ;
146 old_cpsr.c = CondCodesC;
147 old_cpsr.v = CondCodesV;
148 old_cpsr.ge = CondCodesGE;
149
150 CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
151 true, sctlr.nmfi, xc->tcBase());
152 Cpsr = ~CondCodesMask & new_cpsr;
153 CondCodesNZ = new_cpsr.nz;
154 CondCodesC = new_cpsr.c;
155 CondCodesV = new_cpsr.v;
156 CondCodesGE = new_cpsr.ge;
157
158 NextThumb = (new_cpsr).t;
159 NextJazelle = (new_cpsr).j;
160 NextItState = (((new_cpsr).it2 << 2) & 0xFC)
161 | ((new_cpsr).it1 & 0x3);
162
163 NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
164 '''
165
166 eretIop = InstObjParams("eret", "Eret", "PredOp",
167 { "code": eretCode,
168 "predicate_test": predicateTest },
169 ["IsNonSpeculative", "IsSerializeAfter",
170 "IsSquashAfter"])
171 header_output += BasicDeclare.subst(eretIop)
172 decoder_output += BasicConstructor.subst(eretIop)
173 exec_output += PredOpExecute.subst(eretIop)
174
175 crcCode = '''
176 constexpr uint8_t size_bytes = %(sz)d;
177 constexpr uint32_t poly = %(polynom)s;
178
179 uint32_t data = htole(Op2);
180 auto data_buffer = reinterpret_cast<uint8_t*>(&data);
181
182 Dest = crc32<poly>(
183 data_buffer, /* Message Register */
184 Op1, /* Initial Value of the CRC */
185 size_bytes /* Size of the original Message */
186 );
187 '''
188
189 def crc32Emit(mnem, implCode, castagnoli, size):
190 global header_output, decoder_output, exec_output
191
192 if castagnoli:
193 # crc32c instructions
194 poly = "0x1EDC6F41"
195 else:
196 # crc32 instructions
197 poly = "0x04C11DB7"
198
199 data = {'sz' : size, 'polynom': poly}
200
201 instCode = implCode % data
202
203 crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
204 { "code": instCode,
205 "predicate_test": predicateTest }, [])
206 header_output += RegRegRegOpDeclare.subst(crcIop)
207 decoder_output += RegRegRegOpConstructor.subst(crcIop)
208 exec_output += PredOpExecute.subst(crcIop)
209
210 crc32Emit("crc32b", crcCode, False, 1);
211 crc32Emit("crc32h", crcCode, False, 2);
212 crc32Emit("crc32w", crcCode, False, 4);
213 crc32Emit("crc32cb", crcCode, True, 1);
214 crc32Emit("crc32ch", crcCode, True, 2);
215 crc32Emit("crc32cw", crcCode, True, 4);
216
217}};
218
219let {{
220
221 header_output = decoder_output = exec_output = ""
222
223 mrsCpsrCode = '''
224 CPSR cpsr = Cpsr;
225 cpsr.nz = CondCodesNZ;
226 cpsr.c = CondCodesC;
227 cpsr.v = CondCodesV;
228 cpsr.ge = CondCodesGE;
229 Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
230 '''
231
232 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
233 { "code": mrsCpsrCode,
234 "predicate_test": condPredicateTest },
235 ["IsSerializeBefore"])
236 header_output += MrsDeclare.subst(mrsCpsrIop)
237 decoder_output += MrsConstructor.subst(mrsCpsrIop)
238 exec_output += PredOpExecute.subst(mrsCpsrIop)
239
240 mrsSpsrCode = "Dest = Spsr"
241 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
242 { "code": mrsSpsrCode,
243 "predicate_test": predicateTest },
244 ["IsSerializeBefore"])
245 header_output += MrsDeclare.subst(mrsSpsrIop)
246 decoder_output += MrsConstructor.subst(mrsSpsrIop)
247 exec_output += PredOpExecute.subst(mrsSpsrIop)
248
249 mrsBankedRegCode = '''
250 bool isIntReg;
251 int regIdx;
252
253 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
254 if (isIntReg) {
255 Dest = DecodedBankedIntReg;
256 } else {
257 Dest = xc->readMiscReg(regIdx);
258 }
259 } else {
260 return std::make_shared<UndefinedInstruction>(machInst, false,
261 mnemonic);
262 }
263 '''
264 mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
265 { "code": mrsBankedRegCode,
266 "predicate_test": predicateTest },
267 ["IsSerializeBefore"])
268 header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
269 decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
270 exec_output += PredOpExecute.subst(mrsBankedRegIop)
271
272 msrBankedRegCode = '''
273 bool isIntReg;
274 int regIdx;
275
276 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
277 if (isIntReg) {
278 // This is a bit nasty, you would have thought that
279 // DecodedBankedIntReg wouldn't be written to unless the
280 // conditions on the IF statements above are met, however if
281 // you look at the generated C code you'll find that they are.
282 // However this is safe as DecodedBankedIntReg (which is used
283 // in operands.isa to get the index of DecodedBankedIntReg)
284 // will return INTREG_DUMMY if its not a valid integer
285 // register, so redirecting the write to somewhere we don't
286 // care about.
287 DecodedBankedIntReg = Op1;
288 } else {
289 xc->setMiscReg(regIdx, Op1);
290 }
291 } else {
292 return std::make_shared<UndefinedInstruction>(machInst, false,
293 mnemonic);
294 }
295 '''
296 msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
297 { "code": msrBankedRegCode,
298 "predicate_test": predicateTest },
299 ["IsSerializeAfter", "IsNonSpeculative"])
300 header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
301 decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
302 exec_output += PredOpExecute.subst(msrBankedRegIop)
303
304 msrCpsrRegCode = '''
305 SCTLR sctlr = Sctlr;
306 CPSR old_cpsr = Cpsr;
307 old_cpsr.nz = CondCodesNZ;
308 old_cpsr.c = CondCodesC;
309 old_cpsr.v = CondCodesV;
310 old_cpsr.ge = CondCodesGE;
311
312 CPSR new_cpsr =
313 cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
314 sctlr.nmfi, xc->tcBase());
315 Cpsr = ~CondCodesMask & new_cpsr;
316 CondCodesNZ = new_cpsr.nz;
317 CondCodesC = new_cpsr.c;
318 CondCodesV = new_cpsr.v;
319 CondCodesGE = new_cpsr.ge;
320 '''
321 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
322 { "code": msrCpsrRegCode,
323 "predicate_test": condPredicateTest },
324 ["IsSerializeAfter","IsNonSpeculative"])
325 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
326 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
327 exec_output += PredOpExecute.subst(msrCpsrRegIop)
328
329 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
330 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
331 { "code": msrSpsrRegCode,
332 "predicate_test": predicateTest },
333 ["IsSerializeAfter","IsNonSpeculative"])
334 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
335 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
336 exec_output += PredOpExecute.subst(msrSpsrRegIop)
337
338 msrCpsrImmCode = '''
339 SCTLR sctlr = Sctlr;
340 CPSR old_cpsr = Cpsr;
341 old_cpsr.nz = CondCodesNZ;
342 old_cpsr.c = CondCodesC;
343 old_cpsr.v = CondCodesV;
344 old_cpsr.ge = CondCodesGE;
345 CPSR new_cpsr =
346 cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
347 sctlr.nmfi, xc->tcBase());
348 Cpsr = ~CondCodesMask & new_cpsr;
349 CondCodesNZ = new_cpsr.nz;
350 CondCodesC = new_cpsr.c;
351 CondCodesV = new_cpsr.v;
352 CondCodesGE = new_cpsr.ge;
353 '''
354 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
355 { "code": msrCpsrImmCode,
356 "predicate_test": condPredicateTest },
357 ["IsSerializeAfter","IsNonSpeculative"])
358 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
359 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
360 exec_output += PredOpExecute.subst(msrCpsrImmIop)
361
362 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
363 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
364 { "code": msrSpsrImmCode,
365 "predicate_test": predicateTest },
366 ["IsSerializeAfter","IsNonSpeculative"])
367 header_output += MsrImmDeclare.subst(msrSpsrImmIop)
368 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
369 exec_output += PredOpExecute.subst(msrSpsrImmIop)
370
371 revCode = '''
372 uint32_t val = Op1;
373 Dest = swap_byte(val);
374 '''
375 revIop = InstObjParams("rev", "Rev", "RegRegOp",
376 { "code": revCode,
377 "predicate_test": predicateTest }, [])
378 header_output += RegRegOpDeclare.subst(revIop)
379 decoder_output += RegRegOpConstructor.subst(revIop)
380 exec_output += PredOpExecute.subst(revIop)
381
382 rev16Code = '''
383 uint32_t val = Op1;
384 Dest = (bits(val, 15, 8) << 0) |
385 (bits(val, 7, 0) << 8) |
386 (bits(val, 31, 24) << 16) |
387 (bits(val, 23, 16) << 24);
388 '''
389 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
390 { "code": rev16Code,
391 "predicate_test": predicateTest }, [])
392 header_output += RegRegOpDeclare.subst(rev16Iop)
393 decoder_output += RegRegOpConstructor.subst(rev16Iop)
394 exec_output += PredOpExecute.subst(rev16Iop)
395
396 revshCode = '''
397 uint16_t val = Op1;
398 Dest = sext<16>(swap_byte(val));
399 '''
400 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
401 { "code": revshCode,
402 "predicate_test": predicateTest }, [])
403 header_output += RegRegOpDeclare.subst(revshIop)
404 decoder_output += RegRegOpConstructor.subst(revshIop)
405 exec_output += PredOpExecute.subst(revshIop)
406
407 rbitCode = '''
408 Dest = reverseBits(Op1);
409 '''
410 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
411 { "code": rbitCode,
412 "predicate_test": predicateTest }, [])
413 header_output += RegRegOpDeclare.subst(rbitIop)
414 decoder_output += RegRegOpConstructor.subst(rbitIop)
415 exec_output += PredOpExecute.subst(rbitIop)
416
417 clzCode = '''
418 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
419 '''
420 clzIop = InstObjParams("clz", "Clz", "RegRegOp",
421 { "code": clzCode,
422 "predicate_test": predicateTest }, [])
423 header_output += RegRegOpDeclare.subst(clzIop)
424 decoder_output += RegRegOpConstructor.subst(clzIop)
425 exec_output += PredOpExecute.subst(clzIop)
426
427 ssatCode = '''
428 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
429 int32_t res;
430 if (satInt(res, operand, imm))
431 CpsrQ = 1 << 27;
432 Dest = res;
433 '''
434 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
435 { "code": ssatCode,
436 "predicate_test": pickPredicate(ssatCode) }, [])
437 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
438 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
439 exec_output += PredOpExecute.subst(ssatIop)
440
441 usatCode = '''
442 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
443 int32_t res;
444 if (uSatInt(res, operand, imm))
445 CpsrQ = 1 << 27;
446 Dest = res;
447 '''
448 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
449 { "code": usatCode,
450 "predicate_test": pickPredicate(usatCode) }, [])
451 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
452 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
453 exec_output += PredOpExecute.subst(usatIop)
454
455 ssat16Code = '''
456 int32_t res;
457 uint32_t resTemp = 0;
458 int32_t argLow = sext<16>(bits(Op1, 15, 0));
459 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
460 if (satInt(res, argLow, imm))
461 CpsrQ = 1 << 27;
462 replaceBits(resTemp, 15, 0, res);
463 if (satInt(res, argHigh, imm))
464 CpsrQ = 1 << 27;
465 replaceBits(resTemp, 31, 16, res);
466 Dest = resTemp;
467 '''
468 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
469 { "code": ssat16Code,
470 "predicate_test": pickPredicate(ssat16Code) }, [])
471 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
472 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
473 exec_output += PredOpExecute.subst(ssat16Iop)
474
475 usat16Code = '''
476 int32_t res;
477 uint32_t resTemp = 0;
478 int32_t argLow = sext<16>(bits(Op1, 15, 0));
479 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
480 if (uSatInt(res, argLow, imm))
481 CpsrQ = 1 << 27;
482 replaceBits(resTemp, 15, 0, res);
483 if (uSatInt(res, argHigh, imm))
484 CpsrQ = 1 << 27;
485 replaceBits(resTemp, 31, 16, res);
486 Dest = resTemp;
487 '''
488 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
489 { "code": usat16Code,
490 "predicate_test": pickPredicate(usat16Code) }, [])
491 header_output += RegImmRegOpDeclare.subst(usat16Iop)
492 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
493 exec_output += PredOpExecute.subst(usat16Iop)
494
495 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
496 { "code":
497 "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
498 "predicate_test": predicateTest }, [])
499 header_output += RegImmRegOpDeclare.subst(sxtbIop)
500 decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
501 exec_output += PredOpExecute.subst(sxtbIop)
502
503 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
504 { "code":
505 '''
506 Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
507 Op1;
508 ''',
509 "predicate_test": predicateTest }, [])
510 header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
511 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
512 exec_output += PredOpExecute.subst(sxtabIop)
513
514 sxtb16Code = '''
515 uint32_t resTemp = 0;
516 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
517 replaceBits(resTemp, 31, 16,
518 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
519 Dest = resTemp;
520 '''
521 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
522 { "code": sxtb16Code,
523 "predicate_test": predicateTest }, [])
524 header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
525 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
526 exec_output += PredOpExecute.subst(sxtb16Iop)
527
528 sxtab16Code = '''
529 uint32_t resTemp = 0;
530 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
531 bits(Op1, 15, 0));
532 replaceBits(resTemp, 31, 16,
533 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
534 bits(Op1, 31, 16));
535 Dest = resTemp;
536 '''
537 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
538 { "code": sxtab16Code,
539 "predicate_test": predicateTest }, [])
540 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
541 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
542 exec_output += PredOpExecute.subst(sxtab16Iop)
543
544 sxthCode = '''
545 uint64_t rotated = (uint32_t)Op1;
546 rotated = (rotated | (rotated << 32)) >> imm;
547 Dest = sext<16>((uint16_t)rotated);
548 '''
549 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
550 { "code": sxthCode,
551 "predicate_test": predicateTest }, [])
552 header_output += RegImmRegOpDeclare.subst(sxthIop)
553 decoder_output += RegImmRegOpConstructor.subst(sxthIop)
554 exec_output += PredOpExecute.subst(sxthIop)
555
556 sxtahCode = '''
557 uint64_t rotated = (uint32_t)Op2;
558 rotated = (rotated | (rotated << 32)) >> imm;
559 Dest = sext<16>((uint16_t)rotated) + Op1;
560 '''
561 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
562 { "code": sxtahCode,
563 "predicate_test": predicateTest }, [])
564 header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
565 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
566 exec_output += PredOpExecute.subst(sxtahIop)
567
568 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
569 { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
570 "predicate_test": predicateTest }, [])
571 header_output += RegImmRegOpDeclare.subst(uxtbIop)
572 decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
573 exec_output += PredOpExecute.subst(uxtbIop)
574
575 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
576 { "code":
577 "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
578 "predicate_test": predicateTest }, [])
579 header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
580 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
581 exec_output += PredOpExecute.subst(uxtabIop)
582
583 uxtb16Code = '''
584 uint32_t resTemp = 0;
585 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
586 replaceBits(resTemp, 31, 16,
587 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
588 Dest = resTemp;
589 '''
590 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
591 { "code": uxtb16Code,
592 "predicate_test": predicateTest }, [])
593 header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
594 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
595 exec_output += PredOpExecute.subst(uxtb16Iop)
596
597 uxtab16Code = '''
598 uint32_t resTemp = 0;
599 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
600 bits(Op1, 15, 0));
601 replaceBits(resTemp, 31, 16,
602 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
603 bits(Op1, 31, 16));
604 Dest = resTemp;
605 '''
606 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
607 { "code": uxtab16Code,
608 "predicate_test": predicateTest }, [])
609 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
610 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
611 exec_output += PredOpExecute.subst(uxtab16Iop)
612
613 uxthCode = '''
614 uint64_t rotated = (uint32_t)Op1;
615 rotated = (rotated | (rotated << 32)) >> imm;
616 Dest = (uint16_t)rotated;
617 '''
618 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
619 { "code": uxthCode,
620 "predicate_test": predicateTest }, [])
621 header_output += RegImmRegOpDeclare.subst(uxthIop)
622 decoder_output += RegImmRegOpConstructor.subst(uxthIop)
623 exec_output += PredOpExecute.subst(uxthIop)
624
625 uxtahCode = '''
626 uint64_t rotated = (uint32_t)Op2;
627 rotated = (rotated | (rotated << 32)) >> imm;
628 Dest = (uint16_t)rotated + Op1;
629 '''
630 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
631 { "code": uxtahCode,
632 "predicate_test": predicateTest }, [])
633 header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
634 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
635 exec_output += PredOpExecute.subst(uxtahIop)
636
637 selCode = '''
638 uint32_t resTemp = 0;
639 for (unsigned i = 0; i < 4; i++) {
640 int low = i * 8;
641 int high = low + 7;
642 replaceBits(resTemp, high, low,
643 bits(CondCodesGE, i) ?
644 bits(Op1, high, low) : bits(Op2, high, low));
645 }
646 Dest = resTemp;
647 '''
648 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
649 { "code": selCode,
650 "predicate_test": predicateTest }, [])
651 header_output += RegRegRegOpDeclare.subst(selIop)
652 decoder_output += RegRegRegOpConstructor.subst(selIop)
653 exec_output += PredOpExecute.subst(selIop)
654
655 usad8Code = '''
656 uint32_t resTemp = 0;
657 for (unsigned i = 0; i < 4; i++) {
658 int low = i * 8;
659 int high = low + 7;
660 int32_t diff = bits(Op1, high, low) -
661 bits(Op2, high, low);
662 resTemp += ((diff < 0) ? -diff : diff);
663 }
664 Dest = resTemp;
665 '''
666 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
667 { "code": usad8Code,
668 "predicate_test": predicateTest }, [])
669 header_output += RegRegRegOpDeclare.subst(usad8Iop)
670 decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
671 exec_output += PredOpExecute.subst(usad8Iop)
672
673 usada8Code = '''
674 uint32_t resTemp = 0;
675 for (unsigned i = 0; i < 4; i++) {
676 int low = i * 8;
677 int high = low + 7;
678 int32_t diff = bits(Op1, high, low) -
679 bits(Op2, high, low);
680 resTemp += ((diff < 0) ? -diff : diff);
681 }
682 Dest = Op3 + resTemp;
683 '''
684 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
685 { "code": usada8Code,
686 "predicate_test": predicateTest }, [])
687 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
688 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
689 exec_output += PredOpExecute.subst(usada8Iop)
690
691 bkptCode = '''
692 uint16_t imm16;
693 if (!machInst.thumb)
694 imm16 = ((bits(machInst, 19, 8) << 4) | bits(machInst, 3, 0));
695 else
696 imm16 = bits(machInst, 7, 0);
697
698 return softwareBreakpoint32(xc, imm16);
699 '''
700 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
701 header_output += BasicDeclare.subst(bkptIop)
702 decoder_output += BasicConstructor.subst(bkptIop)
703 exec_output += BasicExecute.subst(bkptIop)
704
705 nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
706 header_output += BasicDeclare.subst(nopIop)
707 decoder_output += BasicConstructor64.subst(nopIop)
708 exec_output += BasicExecute.subst(nopIop)
709
710 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
711 { "code" : "", "predicate_test" : predicateTest })
712 header_output += BasicDeclare.subst(yieldIop)
713 decoder_output += BasicConstructor.subst(yieldIop)
714 exec_output += PredOpExecute.subst(yieldIop)
715
716 wfeCode = '''
717 CPSR cpsr = Cpsr;
718 SCR scr = Scr64;
719
720 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
721 ThreadContext *tc = xc->tcBase();
722 if (SevMailbox == 1) {
723 SevMailbox = 0;
724 PseudoInst::quiesceSkip(tc);
725 } else if (tc->getCpuPtr()->getInterruptController(
726 tc->threadId())->checkInterrupts(tc)) {
727 PseudoInst::quiesceSkip(tc);
728 } else {
729 fault = trapWFx(tc, cpsr, scr, true);
730 if (fault == NoFault) {
731 PseudoInst::quiesce(tc);
732 } else {
733 PseudoInst::quiesceSkip(tc);
734 }
735 }
736 '''
737 wfePredFixUpCode = '''
738 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
739 // and SEV interrupts
740 SevMailbox = 1;
741 '''
742 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
743 { "code" : wfeCode,
744 "pred_fixup" : wfePredFixUpCode,
745 "predicate_test" : predicateTest },
746 ["IsNonSpeculative", "IsQuiesce",
747 "IsSerializeAfter", "IsUnverifiable"])
748 header_output += BasicDeclare.subst(wfeIop)
749 decoder_output += BasicConstructor.subst(wfeIop)
750 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
751
752 wfiCode = '''
753 HCR hcr = Hcr;
754 CPSR cpsr = Cpsr;
755 SCR scr = Scr64;
756
757 // WFI doesn't sleep if interrupts are pending (masked or not)
758 ThreadContext *tc = xc->tcBase();
759 if (tc->getCpuPtr()->getInterruptController(
760 tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
761 PseudoInst::quiesceSkip(tc);
762 } else {
763 fault = trapWFx(tc, cpsr, scr, false);
764 if (fault == NoFault) {
765 PseudoInst::quiesce(tc);
766 } else {
767 PseudoInst::quiesceSkip(tc);
768 }
769 }
770 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
771 '''
772 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
773 { "code" : wfiCode, "predicate_test" : predicateTest },
774 ["IsNonSpeculative", "IsQuiesce",
775 "IsSerializeAfter", "IsUnverifiable"])
776 header_output += BasicDeclare.subst(wfiIop)
777 decoder_output += BasicConstructor.subst(wfiIop)
778 exec_output += QuiescePredOpExecute.subst(wfiIop)
779
780 sevCode = '''
781 SevMailbox = 1;
782 System *sys = xc->tcBase()->getSystemPtr();
783 for (int x = 0; x < sys->numContexts(); x++) {
784 ThreadContext *oc = sys->getThreadContext(x);
785 if (oc == xc->tcBase())
786 continue;
787 // Wake CPU with interrupt if they were sleeping
788 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
789 // Post Interrupt and wake cpu if needed
790 oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
791 }
792 }
793 '''
794 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
795 { "code" : sevCode, "predicate_test" : predicateTest },
796 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
797 header_output += BasicDeclare.subst(sevIop)
798 decoder_output += BasicConstructor.subst(sevIop)
799 exec_output += PredOpExecute.subst(sevIop)
800
801 sevlCode = '''
802 SevMailbox = 1;
803 '''
804 sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
805 { "code" : sevlCode, "predicate_test" : predicateTest },
806 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
807 header_output += BasicDeclare.subst(sevlIop)
808 decoder_output += BasicConstructor.subst(sevlIop)
809 exec_output += BasicExecute.subst(sevlIop)
810
811 itIop = InstObjParams("it", "ItInst", "PredOp", \
812 { "code" : ";",
813 "predicate_test" : predicateTest }, [])
814 header_output += BasicDeclare.subst(itIop)
815 decoder_output += BasicConstructor.subst(itIop)
816 exec_output += PredOpExecute.subst(itIop)
817 unknownCode = '''
818 return std::make_shared<UndefinedInstruction>(machInst, true);
819 '''
820 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
821 { "code": unknownCode,
822 "predicate_test": predicateTest })
823 header_output += BasicDeclare.subst(unknownIop)
824 decoder_output += BasicConstructor.subst(unknownIop)
825 exec_output += PredOpExecute.subst(unknownIop)
826
827 ubfxCode = '''
828 Dest = bits(Op1, imm2, imm1);
829 '''
830 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
831 { "code": ubfxCode,
832 "predicate_test": predicateTest }, [])
833 header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
834 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
835 exec_output += PredOpExecute.subst(ubfxIop)
836
837 sbfxCode = '''
838 int32_t resTemp = bits(Op1, imm2, imm1);
839 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
840 '''
841 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
842 { "code": sbfxCode,
843 "predicate_test": predicateTest }, [])
844 header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
845 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
846 exec_output += PredOpExecute.subst(sbfxIop)
847
848 bfcCode = '''
849 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
850 '''
851 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
852 { "code": bfcCode,
853 "predicate_test": predicateTest }, [])
854 header_output += RegRegImmImmOpDeclare.subst(bfcIop)
855 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
856 exec_output += PredOpExecute.subst(bfcIop)
857
858 bfiCode = '''
859 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
860 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
861 '''
862 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
863 { "code": bfiCode,
864 "predicate_test": predicateTest }, [])
865 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
866 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
867 exec_output += PredOpExecute.subst(bfiIop)
868
869 mrc14code = '''
870 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
871 RegId(MiscRegClass, op1)).index();
872 bool can_read, undefined;
873 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
874 if (!can_read || undefined) {
875 return std::make_shared<UndefinedInstruction>(machInst, false,
876 mnemonic);
877 }
878 if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
879 Hstr, Hcptr, imm)) {
880 return std::make_shared<HypervisorTrap>(machInst, imm,
881 EC_TRAPPED_CP14_MCR_MRC);
882 }
883 Dest = MiscOp1;
884 '''
885
886 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
887 { "code": mrc14code,
888 "predicate_test": predicateTest }, [])
889 header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop)
890 decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop)
891 exec_output += PredOpExecute.subst(mrc14Iop)
892
893
894 mcr14code = '''
895 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
896 RegId(MiscRegClass, dest)).index();
897 bool can_write, undefined;
898 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
899 if (undefined || !can_write) {
900 return std::make_shared<UndefinedInstruction>(machInst, false,
901 mnemonic);
902 }
903 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
904 Hstr, Hcptr, imm)) {
905 return std::make_shared<HypervisorTrap>(machInst, imm,
906 EC_TRAPPED_CP14_MCR_MRC);
907 }
908 MiscDest = Op1;
909 '''
910 mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
911 { "code": mcr14code,
912 "predicate_test": predicateTest },
913 ["IsSerializeAfter","IsNonSpeculative"])
914 header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop)
915 decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
916 exec_output += PredOpExecute.subst(mcr14Iop)
917
918 mrc15code = '''
919 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
920 MiscRegIndex miscReg = (MiscRegIndex)
921 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
922 preFlatOp1)).index();
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
43 ThreadContext *tc = xc->tcBase();
44
45 const auto semihost_imm = Thumb? 0xAB : 0x123456;
46
47 if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
48 R0 = ArmSystem::callSemihosting32(tc, R0, R1);
49 } else {
50 fault = std::make_shared<SupervisorCall>(machInst, imm);
51 }
52 '''
53
54 svcIop = InstObjParams("svc", "Svc", "ImmOp",
55 { "code": svcCode,
56 "predicate_test": predicateTest,
57 "thumb_semihost": '0xAB',
58 "arm_semihost": '0x123456' },
59 ["IsSyscall", "IsNonSpeculative",
60 "IsSerializeAfter"])
61 header_output = ImmOpDeclare.subst(svcIop)
62 decoder_output = SemihostConstructor.subst(svcIop)
63 exec_output = PredOpExecute.subst(svcIop)
64
65 hltCode = '''
66 ThreadContext *tc = xc->tcBase();
67
68 const auto semihost_imm = Thumb? 0x3C : 0xF000;
69
70 if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
71 R0 = ArmSystem::callSemihosting32(tc, R0, R1);
72 } else {
73 // HLT instructions aren't implemented, so treat them as undefined
74 // instructions.
75 fault = std::make_shared<UndefinedInstruction>(
76 machInst, false, mnemonic);
77 }
78 '''
79
80 hltIop = InstObjParams("hlt", "Hlt", "ImmOp",
81 { "code": hltCode,
82 "predicate_test": predicateTest,
83 "thumb_semihost": '0x3C',
84 "arm_semihost": '0xF000' },
85 ["IsNonSpeculative"])
86 header_output += ImmOpDeclare.subst(hltIop)
87 decoder_output += SemihostConstructor.subst(hltIop)
88 exec_output += PredOpExecute.subst(hltIop)
89
90 smcCode = '''
91 HCR hcr = Hcr;
92 CPSR cpsr = Cpsr;
93 SCR scr = Scr;
94
95 if ((cpsr.mode != MODE_USER) && FullSystem) {
96 if (ArmSystem::haveVirtualization(xc->tcBase()) &&
97 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
98 fault = std::make_shared<HypervisorTrap>(machInst, 0,
99 EC_SMC_TO_HYP);
100 } else {
101 if (scr.scd) {
102 fault = disabledFault();
103 } else {
104 fault = std::make_shared<SecureMonitorCall>(machInst);
105 }
106 }
107 } else {
108 fault = disabledFault();
109 }
110 '''
111
112 smcIop = InstObjParams("smc", "Smc", "PredOp",
113 { "code": smcCode,
114 "predicate_test": predicateTest },
115 ["IsNonSpeculative", "IsSerializeAfter"])
116 header_output += BasicDeclare.subst(smcIop)
117 decoder_output += BasicConstructor.subst(smcIop)
118 exec_output += PredOpExecute.subst(smcIop)
119
120 hvcCode = '''
121 CPSR cpsr = Cpsr;
122 SCR scr = Scr;
123
124 // Filter out the various cases where this instruction isn't defined
125 if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
126 (cpsr.mode == MODE_USER) ||
127 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
128 fault = disabledFault();
129 } else {
130 fault = std::make_shared<HypervisorCall>(machInst, imm);
131 }
132 '''
133
134 hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
135 { "code": hvcCode,
136 "predicate_test": predicateTest },
137 ["IsNonSpeculative", "IsSerializeAfter"])
138 header_output += ImmOpDeclare.subst(hvcIop)
139 decoder_output += ImmOpConstructor.subst(hvcIop)
140 exec_output += PredOpExecute.subst(hvcIop)
141
142 eretCode = '''
143 SCTLR sctlr = Sctlr;
144 CPSR old_cpsr = Cpsr;
145 old_cpsr.nz = CondCodesNZ;
146 old_cpsr.c = CondCodesC;
147 old_cpsr.v = CondCodesV;
148 old_cpsr.ge = CondCodesGE;
149
150 CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
151 true, sctlr.nmfi, xc->tcBase());
152 Cpsr = ~CondCodesMask & new_cpsr;
153 CondCodesNZ = new_cpsr.nz;
154 CondCodesC = new_cpsr.c;
155 CondCodesV = new_cpsr.v;
156 CondCodesGE = new_cpsr.ge;
157
158 NextThumb = (new_cpsr).t;
159 NextJazelle = (new_cpsr).j;
160 NextItState = (((new_cpsr).it2 << 2) & 0xFC)
161 | ((new_cpsr).it1 & 0x3);
162
163 NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
164 '''
165
166 eretIop = InstObjParams("eret", "Eret", "PredOp",
167 { "code": eretCode,
168 "predicate_test": predicateTest },
169 ["IsNonSpeculative", "IsSerializeAfter",
170 "IsSquashAfter"])
171 header_output += BasicDeclare.subst(eretIop)
172 decoder_output += BasicConstructor.subst(eretIop)
173 exec_output += PredOpExecute.subst(eretIop)
174
175 crcCode = '''
176 constexpr uint8_t size_bytes = %(sz)d;
177 constexpr uint32_t poly = %(polynom)s;
178
179 uint32_t data = htole(Op2);
180 auto data_buffer = reinterpret_cast<uint8_t*>(&data);
181
182 Dest = crc32<poly>(
183 data_buffer, /* Message Register */
184 Op1, /* Initial Value of the CRC */
185 size_bytes /* Size of the original Message */
186 );
187 '''
188
189 def crc32Emit(mnem, implCode, castagnoli, size):
190 global header_output, decoder_output, exec_output
191
192 if castagnoli:
193 # crc32c instructions
194 poly = "0x1EDC6F41"
195 else:
196 # crc32 instructions
197 poly = "0x04C11DB7"
198
199 data = {'sz' : size, 'polynom': poly}
200
201 instCode = implCode % data
202
203 crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
204 { "code": instCode,
205 "predicate_test": predicateTest }, [])
206 header_output += RegRegRegOpDeclare.subst(crcIop)
207 decoder_output += RegRegRegOpConstructor.subst(crcIop)
208 exec_output += PredOpExecute.subst(crcIop)
209
210 crc32Emit("crc32b", crcCode, False, 1);
211 crc32Emit("crc32h", crcCode, False, 2);
212 crc32Emit("crc32w", crcCode, False, 4);
213 crc32Emit("crc32cb", crcCode, True, 1);
214 crc32Emit("crc32ch", crcCode, True, 2);
215 crc32Emit("crc32cw", crcCode, True, 4);
216
217}};
218
219let {{
220
221 header_output = decoder_output = exec_output = ""
222
223 mrsCpsrCode = '''
224 CPSR cpsr = Cpsr;
225 cpsr.nz = CondCodesNZ;
226 cpsr.c = CondCodesC;
227 cpsr.v = CondCodesV;
228 cpsr.ge = CondCodesGE;
229 Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
230 '''
231
232 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
233 { "code": mrsCpsrCode,
234 "predicate_test": condPredicateTest },
235 ["IsSerializeBefore"])
236 header_output += MrsDeclare.subst(mrsCpsrIop)
237 decoder_output += MrsConstructor.subst(mrsCpsrIop)
238 exec_output += PredOpExecute.subst(mrsCpsrIop)
239
240 mrsSpsrCode = "Dest = Spsr"
241 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
242 { "code": mrsSpsrCode,
243 "predicate_test": predicateTest },
244 ["IsSerializeBefore"])
245 header_output += MrsDeclare.subst(mrsSpsrIop)
246 decoder_output += MrsConstructor.subst(mrsSpsrIop)
247 exec_output += PredOpExecute.subst(mrsSpsrIop)
248
249 mrsBankedRegCode = '''
250 bool isIntReg;
251 int regIdx;
252
253 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
254 if (isIntReg) {
255 Dest = DecodedBankedIntReg;
256 } else {
257 Dest = xc->readMiscReg(regIdx);
258 }
259 } else {
260 return std::make_shared<UndefinedInstruction>(machInst, false,
261 mnemonic);
262 }
263 '''
264 mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
265 { "code": mrsBankedRegCode,
266 "predicate_test": predicateTest },
267 ["IsSerializeBefore"])
268 header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
269 decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
270 exec_output += PredOpExecute.subst(mrsBankedRegIop)
271
272 msrBankedRegCode = '''
273 bool isIntReg;
274 int regIdx;
275
276 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
277 if (isIntReg) {
278 // This is a bit nasty, you would have thought that
279 // DecodedBankedIntReg wouldn't be written to unless the
280 // conditions on the IF statements above are met, however if
281 // you look at the generated C code you'll find that they are.
282 // However this is safe as DecodedBankedIntReg (which is used
283 // in operands.isa to get the index of DecodedBankedIntReg)
284 // will return INTREG_DUMMY if its not a valid integer
285 // register, so redirecting the write to somewhere we don't
286 // care about.
287 DecodedBankedIntReg = Op1;
288 } else {
289 xc->setMiscReg(regIdx, Op1);
290 }
291 } else {
292 return std::make_shared<UndefinedInstruction>(machInst, false,
293 mnemonic);
294 }
295 '''
296 msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
297 { "code": msrBankedRegCode,
298 "predicate_test": predicateTest },
299 ["IsSerializeAfter", "IsNonSpeculative"])
300 header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
301 decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
302 exec_output += PredOpExecute.subst(msrBankedRegIop)
303
304 msrCpsrRegCode = '''
305 SCTLR sctlr = Sctlr;
306 CPSR old_cpsr = Cpsr;
307 old_cpsr.nz = CondCodesNZ;
308 old_cpsr.c = CondCodesC;
309 old_cpsr.v = CondCodesV;
310 old_cpsr.ge = CondCodesGE;
311
312 CPSR new_cpsr =
313 cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
314 sctlr.nmfi, xc->tcBase());
315 Cpsr = ~CondCodesMask & new_cpsr;
316 CondCodesNZ = new_cpsr.nz;
317 CondCodesC = new_cpsr.c;
318 CondCodesV = new_cpsr.v;
319 CondCodesGE = new_cpsr.ge;
320 '''
321 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
322 { "code": msrCpsrRegCode,
323 "predicate_test": condPredicateTest },
324 ["IsSerializeAfter","IsNonSpeculative"])
325 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
326 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
327 exec_output += PredOpExecute.subst(msrCpsrRegIop)
328
329 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
330 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
331 { "code": msrSpsrRegCode,
332 "predicate_test": predicateTest },
333 ["IsSerializeAfter","IsNonSpeculative"])
334 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
335 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
336 exec_output += PredOpExecute.subst(msrSpsrRegIop)
337
338 msrCpsrImmCode = '''
339 SCTLR sctlr = Sctlr;
340 CPSR old_cpsr = Cpsr;
341 old_cpsr.nz = CondCodesNZ;
342 old_cpsr.c = CondCodesC;
343 old_cpsr.v = CondCodesV;
344 old_cpsr.ge = CondCodesGE;
345 CPSR new_cpsr =
346 cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
347 sctlr.nmfi, xc->tcBase());
348 Cpsr = ~CondCodesMask & new_cpsr;
349 CondCodesNZ = new_cpsr.nz;
350 CondCodesC = new_cpsr.c;
351 CondCodesV = new_cpsr.v;
352 CondCodesGE = new_cpsr.ge;
353 '''
354 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
355 { "code": msrCpsrImmCode,
356 "predicate_test": condPredicateTest },
357 ["IsSerializeAfter","IsNonSpeculative"])
358 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
359 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
360 exec_output += PredOpExecute.subst(msrCpsrImmIop)
361
362 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
363 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
364 { "code": msrSpsrImmCode,
365 "predicate_test": predicateTest },
366 ["IsSerializeAfter","IsNonSpeculative"])
367 header_output += MsrImmDeclare.subst(msrSpsrImmIop)
368 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
369 exec_output += PredOpExecute.subst(msrSpsrImmIop)
370
371 revCode = '''
372 uint32_t val = Op1;
373 Dest = swap_byte(val);
374 '''
375 revIop = InstObjParams("rev", "Rev", "RegRegOp",
376 { "code": revCode,
377 "predicate_test": predicateTest }, [])
378 header_output += RegRegOpDeclare.subst(revIop)
379 decoder_output += RegRegOpConstructor.subst(revIop)
380 exec_output += PredOpExecute.subst(revIop)
381
382 rev16Code = '''
383 uint32_t val = Op1;
384 Dest = (bits(val, 15, 8) << 0) |
385 (bits(val, 7, 0) << 8) |
386 (bits(val, 31, 24) << 16) |
387 (bits(val, 23, 16) << 24);
388 '''
389 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
390 { "code": rev16Code,
391 "predicate_test": predicateTest }, [])
392 header_output += RegRegOpDeclare.subst(rev16Iop)
393 decoder_output += RegRegOpConstructor.subst(rev16Iop)
394 exec_output += PredOpExecute.subst(rev16Iop)
395
396 revshCode = '''
397 uint16_t val = Op1;
398 Dest = sext<16>(swap_byte(val));
399 '''
400 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
401 { "code": revshCode,
402 "predicate_test": predicateTest }, [])
403 header_output += RegRegOpDeclare.subst(revshIop)
404 decoder_output += RegRegOpConstructor.subst(revshIop)
405 exec_output += PredOpExecute.subst(revshIop)
406
407 rbitCode = '''
408 Dest = reverseBits(Op1);
409 '''
410 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
411 { "code": rbitCode,
412 "predicate_test": predicateTest }, [])
413 header_output += RegRegOpDeclare.subst(rbitIop)
414 decoder_output += RegRegOpConstructor.subst(rbitIop)
415 exec_output += PredOpExecute.subst(rbitIop)
416
417 clzCode = '''
418 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
419 '''
420 clzIop = InstObjParams("clz", "Clz", "RegRegOp",
421 { "code": clzCode,
422 "predicate_test": predicateTest }, [])
423 header_output += RegRegOpDeclare.subst(clzIop)
424 decoder_output += RegRegOpConstructor.subst(clzIop)
425 exec_output += PredOpExecute.subst(clzIop)
426
427 ssatCode = '''
428 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
429 int32_t res;
430 if (satInt(res, operand, imm))
431 CpsrQ = 1 << 27;
432 Dest = res;
433 '''
434 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
435 { "code": ssatCode,
436 "predicate_test": pickPredicate(ssatCode) }, [])
437 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
438 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
439 exec_output += PredOpExecute.subst(ssatIop)
440
441 usatCode = '''
442 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
443 int32_t res;
444 if (uSatInt(res, operand, imm))
445 CpsrQ = 1 << 27;
446 Dest = res;
447 '''
448 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
449 { "code": usatCode,
450 "predicate_test": pickPredicate(usatCode) }, [])
451 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
452 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
453 exec_output += PredOpExecute.subst(usatIop)
454
455 ssat16Code = '''
456 int32_t res;
457 uint32_t resTemp = 0;
458 int32_t argLow = sext<16>(bits(Op1, 15, 0));
459 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
460 if (satInt(res, argLow, imm))
461 CpsrQ = 1 << 27;
462 replaceBits(resTemp, 15, 0, res);
463 if (satInt(res, argHigh, imm))
464 CpsrQ = 1 << 27;
465 replaceBits(resTemp, 31, 16, res);
466 Dest = resTemp;
467 '''
468 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
469 { "code": ssat16Code,
470 "predicate_test": pickPredicate(ssat16Code) }, [])
471 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
472 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
473 exec_output += PredOpExecute.subst(ssat16Iop)
474
475 usat16Code = '''
476 int32_t res;
477 uint32_t resTemp = 0;
478 int32_t argLow = sext<16>(bits(Op1, 15, 0));
479 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
480 if (uSatInt(res, argLow, imm))
481 CpsrQ = 1 << 27;
482 replaceBits(resTemp, 15, 0, res);
483 if (uSatInt(res, argHigh, imm))
484 CpsrQ = 1 << 27;
485 replaceBits(resTemp, 31, 16, res);
486 Dest = resTemp;
487 '''
488 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
489 { "code": usat16Code,
490 "predicate_test": pickPredicate(usat16Code) }, [])
491 header_output += RegImmRegOpDeclare.subst(usat16Iop)
492 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
493 exec_output += PredOpExecute.subst(usat16Iop)
494
495 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
496 { "code":
497 "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
498 "predicate_test": predicateTest }, [])
499 header_output += RegImmRegOpDeclare.subst(sxtbIop)
500 decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
501 exec_output += PredOpExecute.subst(sxtbIop)
502
503 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
504 { "code":
505 '''
506 Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
507 Op1;
508 ''',
509 "predicate_test": predicateTest }, [])
510 header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
511 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
512 exec_output += PredOpExecute.subst(sxtabIop)
513
514 sxtb16Code = '''
515 uint32_t resTemp = 0;
516 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
517 replaceBits(resTemp, 31, 16,
518 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
519 Dest = resTemp;
520 '''
521 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
522 { "code": sxtb16Code,
523 "predicate_test": predicateTest }, [])
524 header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
525 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
526 exec_output += PredOpExecute.subst(sxtb16Iop)
527
528 sxtab16Code = '''
529 uint32_t resTemp = 0;
530 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
531 bits(Op1, 15, 0));
532 replaceBits(resTemp, 31, 16,
533 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
534 bits(Op1, 31, 16));
535 Dest = resTemp;
536 '''
537 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
538 { "code": sxtab16Code,
539 "predicate_test": predicateTest }, [])
540 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
541 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
542 exec_output += PredOpExecute.subst(sxtab16Iop)
543
544 sxthCode = '''
545 uint64_t rotated = (uint32_t)Op1;
546 rotated = (rotated | (rotated << 32)) >> imm;
547 Dest = sext<16>((uint16_t)rotated);
548 '''
549 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
550 { "code": sxthCode,
551 "predicate_test": predicateTest }, [])
552 header_output += RegImmRegOpDeclare.subst(sxthIop)
553 decoder_output += RegImmRegOpConstructor.subst(sxthIop)
554 exec_output += PredOpExecute.subst(sxthIop)
555
556 sxtahCode = '''
557 uint64_t rotated = (uint32_t)Op2;
558 rotated = (rotated | (rotated << 32)) >> imm;
559 Dest = sext<16>((uint16_t)rotated) + Op1;
560 '''
561 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
562 { "code": sxtahCode,
563 "predicate_test": predicateTest }, [])
564 header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
565 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
566 exec_output += PredOpExecute.subst(sxtahIop)
567
568 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
569 { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
570 "predicate_test": predicateTest }, [])
571 header_output += RegImmRegOpDeclare.subst(uxtbIop)
572 decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
573 exec_output += PredOpExecute.subst(uxtbIop)
574
575 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
576 { "code":
577 "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
578 "predicate_test": predicateTest }, [])
579 header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
580 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
581 exec_output += PredOpExecute.subst(uxtabIop)
582
583 uxtb16Code = '''
584 uint32_t resTemp = 0;
585 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
586 replaceBits(resTemp, 31, 16,
587 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
588 Dest = resTemp;
589 '''
590 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
591 { "code": uxtb16Code,
592 "predicate_test": predicateTest }, [])
593 header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
594 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
595 exec_output += PredOpExecute.subst(uxtb16Iop)
596
597 uxtab16Code = '''
598 uint32_t resTemp = 0;
599 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
600 bits(Op1, 15, 0));
601 replaceBits(resTemp, 31, 16,
602 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
603 bits(Op1, 31, 16));
604 Dest = resTemp;
605 '''
606 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
607 { "code": uxtab16Code,
608 "predicate_test": predicateTest }, [])
609 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
610 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
611 exec_output += PredOpExecute.subst(uxtab16Iop)
612
613 uxthCode = '''
614 uint64_t rotated = (uint32_t)Op1;
615 rotated = (rotated | (rotated << 32)) >> imm;
616 Dest = (uint16_t)rotated;
617 '''
618 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
619 { "code": uxthCode,
620 "predicate_test": predicateTest }, [])
621 header_output += RegImmRegOpDeclare.subst(uxthIop)
622 decoder_output += RegImmRegOpConstructor.subst(uxthIop)
623 exec_output += PredOpExecute.subst(uxthIop)
624
625 uxtahCode = '''
626 uint64_t rotated = (uint32_t)Op2;
627 rotated = (rotated | (rotated << 32)) >> imm;
628 Dest = (uint16_t)rotated + Op1;
629 '''
630 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
631 { "code": uxtahCode,
632 "predicate_test": predicateTest }, [])
633 header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
634 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
635 exec_output += PredOpExecute.subst(uxtahIop)
636
637 selCode = '''
638 uint32_t resTemp = 0;
639 for (unsigned i = 0; i < 4; i++) {
640 int low = i * 8;
641 int high = low + 7;
642 replaceBits(resTemp, high, low,
643 bits(CondCodesGE, i) ?
644 bits(Op1, high, low) : bits(Op2, high, low));
645 }
646 Dest = resTemp;
647 '''
648 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
649 { "code": selCode,
650 "predicate_test": predicateTest }, [])
651 header_output += RegRegRegOpDeclare.subst(selIop)
652 decoder_output += RegRegRegOpConstructor.subst(selIop)
653 exec_output += PredOpExecute.subst(selIop)
654
655 usad8Code = '''
656 uint32_t resTemp = 0;
657 for (unsigned i = 0; i < 4; i++) {
658 int low = i * 8;
659 int high = low + 7;
660 int32_t diff = bits(Op1, high, low) -
661 bits(Op2, high, low);
662 resTemp += ((diff < 0) ? -diff : diff);
663 }
664 Dest = resTemp;
665 '''
666 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
667 { "code": usad8Code,
668 "predicate_test": predicateTest }, [])
669 header_output += RegRegRegOpDeclare.subst(usad8Iop)
670 decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
671 exec_output += PredOpExecute.subst(usad8Iop)
672
673 usada8Code = '''
674 uint32_t resTemp = 0;
675 for (unsigned i = 0; i < 4; i++) {
676 int low = i * 8;
677 int high = low + 7;
678 int32_t diff = bits(Op1, high, low) -
679 bits(Op2, high, low);
680 resTemp += ((diff < 0) ? -diff : diff);
681 }
682 Dest = Op3 + resTemp;
683 '''
684 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
685 { "code": usada8Code,
686 "predicate_test": predicateTest }, [])
687 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
688 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
689 exec_output += PredOpExecute.subst(usada8Iop)
690
691 bkptCode = '''
692 uint16_t imm16;
693 if (!machInst.thumb)
694 imm16 = ((bits(machInst, 19, 8) << 4) | bits(machInst, 3, 0));
695 else
696 imm16 = bits(machInst, 7, 0);
697
698 return softwareBreakpoint32(xc, imm16);
699 '''
700 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
701 header_output += BasicDeclare.subst(bkptIop)
702 decoder_output += BasicConstructor.subst(bkptIop)
703 exec_output += BasicExecute.subst(bkptIop)
704
705 nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
706 header_output += BasicDeclare.subst(nopIop)
707 decoder_output += BasicConstructor64.subst(nopIop)
708 exec_output += BasicExecute.subst(nopIop)
709
710 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
711 { "code" : "", "predicate_test" : predicateTest })
712 header_output += BasicDeclare.subst(yieldIop)
713 decoder_output += BasicConstructor.subst(yieldIop)
714 exec_output += PredOpExecute.subst(yieldIop)
715
716 wfeCode = '''
717 CPSR cpsr = Cpsr;
718 SCR scr = Scr64;
719
720 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
721 ThreadContext *tc = xc->tcBase();
722 if (SevMailbox == 1) {
723 SevMailbox = 0;
724 PseudoInst::quiesceSkip(tc);
725 } else if (tc->getCpuPtr()->getInterruptController(
726 tc->threadId())->checkInterrupts(tc)) {
727 PseudoInst::quiesceSkip(tc);
728 } else {
729 fault = trapWFx(tc, cpsr, scr, true);
730 if (fault == NoFault) {
731 PseudoInst::quiesce(tc);
732 } else {
733 PseudoInst::quiesceSkip(tc);
734 }
735 }
736 '''
737 wfePredFixUpCode = '''
738 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
739 // and SEV interrupts
740 SevMailbox = 1;
741 '''
742 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
743 { "code" : wfeCode,
744 "pred_fixup" : wfePredFixUpCode,
745 "predicate_test" : predicateTest },
746 ["IsNonSpeculative", "IsQuiesce",
747 "IsSerializeAfter", "IsUnverifiable"])
748 header_output += BasicDeclare.subst(wfeIop)
749 decoder_output += BasicConstructor.subst(wfeIop)
750 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
751
752 wfiCode = '''
753 HCR hcr = Hcr;
754 CPSR cpsr = Cpsr;
755 SCR scr = Scr64;
756
757 // WFI doesn't sleep if interrupts are pending (masked or not)
758 ThreadContext *tc = xc->tcBase();
759 if (tc->getCpuPtr()->getInterruptController(
760 tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
761 PseudoInst::quiesceSkip(tc);
762 } else {
763 fault = trapWFx(tc, cpsr, scr, false);
764 if (fault == NoFault) {
765 PseudoInst::quiesce(tc);
766 } else {
767 PseudoInst::quiesceSkip(tc);
768 }
769 }
770 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
771 '''
772 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
773 { "code" : wfiCode, "predicate_test" : predicateTest },
774 ["IsNonSpeculative", "IsQuiesce",
775 "IsSerializeAfter", "IsUnverifiable"])
776 header_output += BasicDeclare.subst(wfiIop)
777 decoder_output += BasicConstructor.subst(wfiIop)
778 exec_output += QuiescePredOpExecute.subst(wfiIop)
779
780 sevCode = '''
781 SevMailbox = 1;
782 System *sys = xc->tcBase()->getSystemPtr();
783 for (int x = 0; x < sys->numContexts(); x++) {
784 ThreadContext *oc = sys->getThreadContext(x);
785 if (oc == xc->tcBase())
786 continue;
787 // Wake CPU with interrupt if they were sleeping
788 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
789 // Post Interrupt and wake cpu if needed
790 oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
791 }
792 }
793 '''
794 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
795 { "code" : sevCode, "predicate_test" : predicateTest },
796 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
797 header_output += BasicDeclare.subst(sevIop)
798 decoder_output += BasicConstructor.subst(sevIop)
799 exec_output += PredOpExecute.subst(sevIop)
800
801 sevlCode = '''
802 SevMailbox = 1;
803 '''
804 sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
805 { "code" : sevlCode, "predicate_test" : predicateTest },
806 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
807 header_output += BasicDeclare.subst(sevlIop)
808 decoder_output += BasicConstructor.subst(sevlIop)
809 exec_output += BasicExecute.subst(sevlIop)
810
811 itIop = InstObjParams("it", "ItInst", "PredOp", \
812 { "code" : ";",
813 "predicate_test" : predicateTest }, [])
814 header_output += BasicDeclare.subst(itIop)
815 decoder_output += BasicConstructor.subst(itIop)
816 exec_output += PredOpExecute.subst(itIop)
817 unknownCode = '''
818 return std::make_shared<UndefinedInstruction>(machInst, true);
819 '''
820 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
821 { "code": unknownCode,
822 "predicate_test": predicateTest })
823 header_output += BasicDeclare.subst(unknownIop)
824 decoder_output += BasicConstructor.subst(unknownIop)
825 exec_output += PredOpExecute.subst(unknownIop)
826
827 ubfxCode = '''
828 Dest = bits(Op1, imm2, imm1);
829 '''
830 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
831 { "code": ubfxCode,
832 "predicate_test": predicateTest }, [])
833 header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
834 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
835 exec_output += PredOpExecute.subst(ubfxIop)
836
837 sbfxCode = '''
838 int32_t resTemp = bits(Op1, imm2, imm1);
839 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
840 '''
841 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
842 { "code": sbfxCode,
843 "predicate_test": predicateTest }, [])
844 header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
845 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
846 exec_output += PredOpExecute.subst(sbfxIop)
847
848 bfcCode = '''
849 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
850 '''
851 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
852 { "code": bfcCode,
853 "predicate_test": predicateTest }, [])
854 header_output += RegRegImmImmOpDeclare.subst(bfcIop)
855 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
856 exec_output += PredOpExecute.subst(bfcIop)
857
858 bfiCode = '''
859 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
860 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
861 '''
862 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
863 { "code": bfiCode,
864 "predicate_test": predicateTest }, [])
865 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
866 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
867 exec_output += PredOpExecute.subst(bfiIop)
868
869 mrc14code = '''
870 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
871 RegId(MiscRegClass, op1)).index();
872 bool can_read, undefined;
873 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
874 if (!can_read || undefined) {
875 return std::make_shared<UndefinedInstruction>(machInst, false,
876 mnemonic);
877 }
878 if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
879 Hstr, Hcptr, imm)) {
880 return std::make_shared<HypervisorTrap>(machInst, imm,
881 EC_TRAPPED_CP14_MCR_MRC);
882 }
883 Dest = MiscOp1;
884 '''
885
886 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
887 { "code": mrc14code,
888 "predicate_test": predicateTest }, [])
889 header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop)
890 decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop)
891 exec_output += PredOpExecute.subst(mrc14Iop)
892
893
894 mcr14code = '''
895 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
896 RegId(MiscRegClass, dest)).index();
897 bool can_write, undefined;
898 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
899 if (undefined || !can_write) {
900 return std::make_shared<UndefinedInstruction>(machInst, false,
901 mnemonic);
902 }
903 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
904 Hstr, Hcptr, imm)) {
905 return std::make_shared<HypervisorTrap>(machInst, imm,
906 EC_TRAPPED_CP14_MCR_MRC);
907 }
908 MiscDest = Op1;
909 '''
910 mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
911 { "code": mcr14code,
912 "predicate_test": predicateTest },
913 ["IsSerializeAfter","IsNonSpeculative"])
914 header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop)
915 decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
916 exec_output += PredOpExecute.subst(mcr14Iop)
917
918 mrc15code = '''
919 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
920 MiscRegIndex miscReg = (MiscRegIndex)
921 xc->tcBase()->flattenRegId(RegId(MiscRegClass,
922 preFlatOp1)).index();
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