1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2012 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 svcCode = '''
43 if (FullSystem) {
44 fault = new SupervisorCall;
45 } else {
46 fault = new SupervisorCall(machInst);
47 }
48 '''
49
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
51 { "code": svcCode,
52 "predicate_test": predicateTest },
53 ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
54 header_output = BasicDeclare.subst(svcIop)
55 decoder_output = BasicConstructor.subst(svcIop)
56 exec_output = PredOpExecute.subst(svcIop)
57
58}};
59
60let {{
61
62 header_output = decoder_output = exec_output = ""
63
64 mrsCpsrCode = '''
65 CPSR cpsr = Cpsr;

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82 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
83 { "code": mrsSpsrCode,
84 "predicate_test": predicateTest },
85 ["IsSerializeBefore"])
86 header_output += MrsDeclare.subst(mrsSpsrIop)
87 decoder_output += MrsConstructor.subst(mrsSpsrIop)
88 exec_output += PredOpExecute.subst(mrsSpsrIop)
89
90 msrCpsrRegCode = '''
91 SCTLR sctlr = Sctlr;
92 CPSR old_cpsr = Cpsr;
93 old_cpsr.nz = CondCodesNZ;
94 old_cpsr.c = CondCodesC;
95 old_cpsr.v = CondCodesV;
96 old_cpsr.ge = CondCodesGE;
97
98 CPSR new_cpsr =
99 cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
100 Cpsr = ~CondCodesMask & new_cpsr;
101 CondCodesNZ = new_cpsr.nz;
102 CondCodesC = new_cpsr.c;
103 CondCodesV = new_cpsr.v;
104 CondCodesGE = new_cpsr.ge;
105 '''
106 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
107 { "code": msrCpsrRegCode,

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123 msrCpsrImmCode = '''
124 SCTLR sctlr = Sctlr;
125 CPSR old_cpsr = Cpsr;
126 old_cpsr.nz = CondCodesNZ;
127 old_cpsr.c = CondCodesC;
128 old_cpsr.v = CondCodesV;
129 old_cpsr.ge = CondCodesGE;
130 CPSR new_cpsr =
131 cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
132 Cpsr = ~CondCodesMask & new_cpsr;
133 CondCodesNZ = new_cpsr.nz;
134 CondCodesC = new_cpsr.c;
135 CondCodesV = new_cpsr.v;
136 CondCodesGE = new_cpsr.ge;
137 '''
138 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
139 { "code": msrCpsrImmCode,

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483 exec_output += PredOpExecute.subst(usada8Iop)
484
485 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
486 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
487 header_output += BasicDeclare.subst(bkptIop)
488 decoder_output += BasicConstructor.subst(bkptIop)
489 exec_output += BasicExecute.subst(bkptIop)
490
491 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
492 { "code" : "", "predicate_test" : predicateTest },
493 ['IsNop'])
494 header_output += BasicDeclare.subst(nopIop)
495 decoder_output += BasicConstructor.subst(nopIop)
496 exec_output += PredOpExecute.subst(nopIop)
497
498 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
499 { "code" : "", "predicate_test" : predicateTest })
500 header_output += BasicDeclare.subst(yieldIop)
501 decoder_output += BasicConstructor.subst(yieldIop)
502 exec_output += PredOpExecute.subst(yieldIop)
503
504 wfeCode = '''
505 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
506 if (SevMailbox == 1) {
507 SevMailbox = 0;
508 PseudoInst::quiesceSkip(xc->tcBase());
509 } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
510 PseudoInst::quiesceSkip(xc->tcBase());
511 } else {
512 PseudoInst::quiesce(xc->tcBase());
513 }
514 '''
515 wfePredFixUpCode = '''
516 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
517 // and SEV interrupts
518 SevMailbox = 1;
519 '''
520 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
521 { "code" : wfeCode,
522 "pred_fixup" : wfePredFixUpCode,
523 "predicate_test" : predicateTest },
524 ["IsNonSpeculative", "IsQuiesce",
525 "IsSerializeAfter", "IsUnverifiable"])
526 header_output += BasicDeclare.subst(wfeIop)
527 decoder_output += BasicConstructor.subst(wfeIop)
528 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
529
530 wfiCode = '''
531 // WFI doesn't sleep if interrupts are pending (masked or not)
532 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
533 PseudoInst::quiesceSkip(xc->tcBase());
534 } else {
535 PseudoInst::quiesce(xc->tcBase());
536 }
537 '''
538 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
539 { "code" : wfiCode, "predicate_test" : predicateTest },
540 ["IsNonSpeculative", "IsQuiesce",
541 "IsSerializeAfter", "IsUnverifiable"])
542 header_output += BasicDeclare.subst(wfiIop)
543 decoder_output += BasicConstructor.subst(wfiIop)
544 exec_output += QuiescePredOpExecute.subst(wfiIop)

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559 '''
560 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
561 { "code" : sevCode, "predicate_test" : predicateTest },
562 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
563 header_output += BasicDeclare.subst(sevIop)
564 decoder_output += BasicConstructor.subst(sevIop)
565 exec_output += PredOpExecute.subst(sevIop)
566
567 itIop = InstObjParams("it", "ItInst", "PredOp", \
568 { "code" : ";",
569 "predicate_test" : predicateTest }, [])
570 header_output += BasicDeclare.subst(itIop)
571 decoder_output += BasicConstructor.subst(itIop)
572 exec_output += PredOpExecute.subst(itIop)
573 unknownCode = '''
574 if (FullSystem)
575 return new UndefinedInstruction;
576 else
577 return new UndefinedInstruction(machInst, true);
578 '''
579 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
580 { "code": unknownCode,
581 "predicate_test": predicateTest })
582 header_output += BasicDeclare.subst(unknownIop)
583 decoder_output += BasicConstructor.subst(unknownIop)
584 exec_output += PredOpExecute.subst(unknownIop)
585

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621 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
622 { "code": bfiCode,
623 "predicate_test": predicateTest }, [])
624 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
625 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
626 exec_output += PredOpExecute.subst(bfiIop)
627
628 mrc14code = '''
629 CPSR cpsr = Cpsr;
630 if (cpsr.mode == MODE_USER) {
631 if (FullSystem)
632 return new UndefinedInstruction;
633 else
634 return new UndefinedInstruction(false, mnemonic);
635 }
636 Dest = MiscOp1;
637 '''
638
639 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegOp",
640 { "code": mrc14code,
641 "predicate_test": predicateTest }, [])
642 header_output += RegRegOpDeclare.subst(mrc14Iop)
643 decoder_output += RegRegOpConstructor.subst(mrc14Iop)
644 exec_output += PredOpExecute.subst(mrc14Iop)
645
646
647 mcr14code = '''
648 CPSR cpsr = Cpsr;
649 if (cpsr.mode == MODE_USER) {
650 if (FullSystem)
651 return new UndefinedInstruction;
652 else
653 return new UndefinedInstruction(false, mnemonic);
654 }
655 MiscDest = Op1;
656 '''
657 mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegOp",
658 { "code": mcr14code,
659 "predicate_test": predicateTest },
660 ["IsSerializeAfter","IsNonSpeculative"])
661 header_output += RegRegOpDeclare.subst(mcr14Iop)
662 decoder_output += RegRegOpConstructor.subst(mcr14Iop)
663 exec_output += PredOpExecute.subst(mcr14Iop)
664
665 mrc14UserIop = InstObjParams("mrc", "Mrc14User", "RegRegOp",
666 { "code": "Dest = MiscOp1;",
667 "predicate_test": predicateTest }, [])
668 header_output += RegRegOpDeclare.subst(mrc14UserIop)
669 decoder_output += RegRegOpConstructor.subst(mrc14UserIop)
670 exec_output += PredOpExecute.subst(mrc14UserIop)
671
672 mcr14UserIop = InstObjParams("mcr", "Mcr14User", "RegRegOp",
673 { "code": "MiscDest = Op1",
674 "predicate_test": predicateTest },
675 ["IsSerializeAfter","IsNonSpeculative"])
676 header_output += RegRegOpDeclare.subst(mcr14UserIop)
677 decoder_output += RegRegOpConstructor.subst(mcr14UserIop)
678 exec_output += PredOpExecute.subst(mcr14UserIop)
679
680 mrc15code = '''
681 CPSR cpsr = Cpsr;
682 if (cpsr.mode == MODE_USER) {
683 if (FullSystem)
684 return new UndefinedInstruction;
685 else
686 return new UndefinedInstruction(false, mnemonic);
687 }
688 Dest = MiscOp1;
689 '''
690
691 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
692 { "code": mrc15code,
693 "predicate_test": predicateTest }, [])
694 header_output += RegRegOpDeclare.subst(mrc15Iop)
695 decoder_output += RegRegOpConstructor.subst(mrc15Iop)
696 exec_output += PredOpExecute.subst(mrc15Iop)
697
698
699 mcr15code = '''
700 CPSR cpsr = Cpsr;
701 if (cpsr.mode == MODE_USER) {
702 if (FullSystem)
703 return new UndefinedInstruction;
704 else
705 return new UndefinedInstruction(false, mnemonic);
706 }
707 MiscDest = Op1;
708 '''
709 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
710 { "code": mcr15code,
711 "predicate_test": predicateTest },
712 ["IsSerializeAfter","IsNonSpeculative"])
713 header_output += RegRegOpDeclare.subst(mcr15Iop)
714 decoder_output += RegRegOpConstructor.subst(mcr15Iop)
715 exec_output += PredOpExecute.subst(mcr15Iop)
716
717 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
718 { "code": "Dest = MiscOp1;",
719 "predicate_test": predicateTest }, [])
720 header_output += RegRegOpDeclare.subst(mrc15UserIop)
721 decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
722 exec_output += PredOpExecute.subst(mrc15UserIop)
723
724 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
725 { "code": "MiscDest = Op1",
726 "predicate_test": predicateTest },
727 ["IsSerializeAfter","IsNonSpeculative"])
728 header_output += RegRegOpDeclare.subst(mcr15UserIop)
729 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
730 exec_output += PredOpExecute.subst(mcr15UserIop)
731
732 enterxCode = '''
733 NextThumb = true;
734 NextJazelle = true;
735 '''
736 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
737 { "code": enterxCode,
738 "predicate_test": predicateTest }, [])
739 header_output += BasicDeclare.subst(enterxIop)

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770 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
771 { "code": clrexCode,
772 "predicate_test": predicateTest },[])
773 header_output += BasicDeclare.subst(clrexIop)
774 decoder_output += BasicConstructor.subst(clrexIop)
775 exec_output += PredOpExecute.subst(clrexIop)
776
777 isbCode = '''
778 fault = new FlushPipe;
779 '''
780 isbIop = InstObjParams("isb", "Isb", "PredOp",
781 {"code": isbCode,
782 "predicate_test": predicateTest},
783 ['IsSerializeAfter'])
784 header_output += BasicDeclare.subst(isbIop)
785 decoder_output += BasicConstructor.subst(isbIop)
786 exec_output += PredOpExecute.subst(isbIop)
787
788 dsbCode = '''
789 fault = new FlushPipe;
790 '''
791 dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
792 {"code": dsbCode,
793 "predicate_test": predicateTest},
794 ['IsMemBarrier', 'IsSerializeAfter'])
795 header_output += BasicDeclare.subst(dsbIop)
796 decoder_output += BasicConstructor.subst(dsbIop)
797 exec_output += PredOpExecute.subst(dsbIop)
798
799 dmbCode = '''
800 '''
801 dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
802 {"code": dmbCode,
803 "predicate_test": predicateTest},
804 ['IsMemBarrier'])
805 header_output += BasicDeclare.subst(dmbIop)
806 decoder_output += BasicConstructor.subst(dmbIop)
807 exec_output += PredOpExecute.subst(dmbIop)
808
809 dbgCode = '''
810 '''
811 dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
812 {"code": dbgCode,
813 "predicate_test": predicateTest})
814 header_output += BasicDeclare.subst(dbgIop)

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