1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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55 exec_output = PredOpExecute.subst(svcIop)
56
57}};
58
59let {{
60
61 header_output = decoder_output = exec_output = ""
62
63 mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
64 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
65 { "code": mrsCpsrCode,
66 "predicate_test": condPredicateTest },
67 ["IsSerializeBefore"])
68 header_output += MrsDeclare.subst(mrsCpsrIop)
69 decoder_output += MrsConstructor.subst(mrsCpsrIop)
70 exec_output += PredOpExecute.subst(mrsCpsrIop)
71

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76 ["IsSerializeBefore"])
77 header_output += MrsDeclare.subst(mrsSpsrIop)
78 decoder_output += MrsConstructor.subst(mrsSpsrIop)
79 exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81 msrCpsrRegCode = '''
82 SCTLR sctlr = Sctlr;
83 uint32_t newCpsr =
84 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85 Cpsr = ~CondCodesMask & newCpsr;
86 CondCodes = CondCodesMask & newCpsr;
87 '''
88 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
89 { "code": msrCpsrRegCode,
90 "predicate_test": condPredicateTest },
91 ["IsSerializeAfter","IsNonSpeculative"])
92 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
93 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
94 exec_output += PredOpExecute.subst(msrCpsrRegIop)

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100 ["IsSerializeAfter","IsNonSpeculative"])
101 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
102 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
103 exec_output += PredOpExecute.subst(msrSpsrRegIop)
104
105 msrCpsrImmCode = '''
106 SCTLR sctlr = Sctlr;
107 uint32_t newCpsr =
108 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
109 Cpsr = ~CondCodesMask & newCpsr;
110 CondCodes = CondCodesMask & newCpsr;
111 '''
112 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
113 { "code": msrCpsrImmCode,
114 "predicate_test": condPredicateTest },
115 ["IsSerializeAfter","IsNonSpeculative"])
116 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
117 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
118 exec_output += PredOpExecute.subst(msrCpsrImmIop)

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191 header_output += RegRegOpDeclare.subst(clzIop)
192 decoder_output += RegRegOpConstructor.subst(clzIop)
193 exec_output += PredOpExecute.subst(clzIop)
194
195 ssatCode = '''
196 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
197 int32_t res;
198 if (satInt(res, operand, imm))
199 CondCodes = CondCodes | (1 << 27);
200 else
201 CondCodes = CondCodes;
202 Dest = res;
203 '''
204 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
205 { "code": ssatCode,
206 "predicate_test": condPredicateTest }, [])
207 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
208 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
209 exec_output += PredOpExecute.subst(ssatIop)
210
211 usatCode = '''
212 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
213 int32_t res;
214 if (uSatInt(res, operand, imm))
215 CondCodes = CondCodes | (1 << 27);
216 else
217 CondCodes = CondCodes;
218 Dest = res;
219 '''
220 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
221 { "code": usatCode,
222 "predicate_test": condPredicateTest }, [])
223 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
224 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
225 exec_output += PredOpExecute.subst(usatIop)
226
227 ssat16Code = '''
228 int32_t res;
229 uint32_t resTemp = 0;
230 CondCodes = CondCodes;
231 int32_t argLow = sext<16>(bits(Op1, 15, 0));
232 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
233 if (satInt(res, argLow, imm))
234 CondCodes = CondCodes | (1 << 27);
235 replaceBits(resTemp, 15, 0, res);
236 if (satInt(res, argHigh, imm))
237 CondCodes = CondCodes | (1 << 27);
238 replaceBits(resTemp, 31, 16, res);
239 Dest = resTemp;
240 '''
241 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
242 { "code": ssat16Code,
243 "predicate_test": condPredicateTest }, [])
244 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
245 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
246 exec_output += PredOpExecute.subst(ssat16Iop)
247
248 usat16Code = '''
249 int32_t res;
250 uint32_t resTemp = 0;
251 CondCodes = CondCodes;
252 int32_t argLow = sext<16>(bits(Op1, 15, 0));
253 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
254 if (uSatInt(res, argLow, imm))
255 CondCodes = CondCodes | (1 << 27);
256 replaceBits(resTemp, 15, 0, res);
257 if (uSatInt(res, argHigh, imm))
258 CondCodes = CondCodes | (1 << 27);
259 replaceBits(resTemp, 31, 16, res);
260 Dest = resTemp;
261 '''
262 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
263 { "code": usat16Code,
264 "predicate_test": condPredicateTest }, [])
265 header_output += RegImmRegOpDeclare.subst(usat16Iop)
266 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)

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409 exec_output += PredOpExecute.subst(uxtahIop)
410
411 selCode = '''
412 uint32_t resTemp = 0;
413 for (unsigned i = 0; i < 4; i++) {
414 int low = i * 8;
415 int high = low + 7;
416 replaceBits(resTemp, high, low,
417 bits(CondCodes, 16 + i) ?
418 bits(Op1, high, low) : bits(Op2, high, low));
419 }
420 Dest = resTemp;
421 '''
422 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
423 { "code": selCode,
424 "predicate_test": condPredicateTest }, [])
425 header_output += RegRegRegOpDeclare.subst(selIop)

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