1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 48 unchanged lines hidden (view full) ---

57 "thumb_semihost": '0xAB',
58 "arm_semihost": '0x123456' },
59 ["IsSyscall", "IsNonSpeculative",
60 "IsSerializeAfter"])
61 header_output = ImmOpDeclare.subst(svcIop)
62 decoder_output = SemihostConstructor.subst(svcIop)
63 exec_output = PredOpExecute.subst(svcIop)
64
65 smcCode = '''
66 HCR hcr = Hcr;
67 CPSR cpsr = Cpsr;
68 SCR scr = Scr;
69
70 if ((cpsr.mode != MODE_USER) && FullSystem) {
71 if (ArmSystem::haveVirtualization(xc->tcBase()) &&
72 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {

--- 1175 unchanged lines hidden ---