1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 def loadStoreBaseWork(name, Name, imm, swp, rfe, srs, codeBlobs, 42 memFlags, instFlags, double, strex, 43 base = 'Memory', execTemplateBase = ''): 44 # Make sure flags are in lists (convert to lists if not). 45 memFlags = makeList(memFlags) 46 instFlags = makeList(instFlags) 47 48 eaCode = codeBlobs["ea_code"] 49 50 # This shouldn't be part of the eaCode, but until the exec templates 51 # are converted over it's the easiest place to put it. 52 eaCode += '\n unsigned memAccessFlags = ' 53 eaCode += (string.join(memFlags, '|') + ';') 54 55 codeBlobs["ea_code"] = eaCode 56 57 iop = InstObjParams(name, Name, base, codeBlobs, instFlags) 58 59 fullExecTemplate = eval(execTemplateBase + 'Execute') 60 initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc') 61 completeAccTemplate = eval(execTemplateBase + 'CompleteAcc') 62 63 if swp: 64 declareTemplate = SwapDeclare 65 constructTemplate = SwapConstructor 66 elif rfe: 67 declareTemplate = RfeDeclare 68 constructTemplate = RfeConstructor 69 elif srs: 70 declareTemplate = SrsDeclare 71 constructTemplate = SrsConstructor 72 elif imm: 73 if double: 74 declareTemplate = LoadStoreDImmDeclare 75 constructTemplate = LoadStoreDImmConstructor 76 if strex: 77 declareTemplate = StoreExDImmDeclare 78 constructTemplate = StoreExDImmConstructor 79 elif strex: 80 declareTemplate = StoreExImmDeclare 81 constructTemplate = StoreExImmConstructor 82 else: 83 declareTemplate = LoadStoreImmDeclare 84 constructTemplate = LoadStoreImmConstructor 85 else: 86 if double: 87 declareTemplate = LoadStoreDRegDeclare 88 constructTemplate = LoadStoreDRegConstructor 89 else: 90 declareTemplate = LoadStoreRegDeclare 91 constructTemplate = LoadStoreRegConstructor 92 93 # (header_output, decoder_output, decode_block, exec_output) 94 return (declareTemplate.subst(iop), 95 constructTemplate.subst(iop), 96 fullExecTemplate.subst(iop) 97 + initiateAccTemplate.subst(iop) 98 + completeAccTemplate.subst(iop)) 99
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100 def pickPredicate(blobs): 101 for val in blobs.values(): 102 if re.search('(?<!Opt)CondCodes', val): 103 return condPredicateTest 104 return predicateTest 105 |
106 def loadStoreBase(name, Name, imm, eaCode, accCode, postAccCode, 107 memFlags, instFlags, double, strex, base = 'Memory', 108 execTemplateBase = ''): 109 codeBlobs = { "ea_code": eaCode, 110 "memacc_code": accCode,
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105 "postacc_code": postAccCode,
106 "predicate_test": predicateTest }
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111 "postacc_code": postAccCode } 112 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) |
113 return loadStoreBaseWork(name, Name, imm, False, False, False, 114 codeBlobs, memFlags, instFlags, double, 115 strex, base, execTemplateBase) 116 117 def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags): 118 codeBlobs = { "ea_code": eaCode,
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113 "memacc_code": accCode,
114 "predicate_test": predicateTest }
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119 "memacc_code": accCode } 120 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) |
121 return loadStoreBaseWork(name, Name, False, False, True, False, 122 codeBlobs, memFlags, instFlags, False, False, 123 'RfeOp', 'Load') 124 125 def SrsBase(name, Name, eaCode, accCode, memFlags, instFlags): 126 codeBlobs = { "ea_code": eaCode, 127 "memacc_code": accCode,
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122 "postacc_code": "",
123 "predicate_test": predicateTest }
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128 "postacc_code": "" } 129 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) |
130 return loadStoreBaseWork(name, Name, False, False, False, True, 131 codeBlobs, memFlags, instFlags, False, False, 132 'SrsOp', 'Store') 133 134 def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags, 135 instFlags): 136 codeBlobs = { "ea_code": eaCode, 137 "preacc_code": preAccCode,
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132 "postacc_code": postAccCode,
133 "predicate_test": predicateTest }
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138 "postacc_code": postAccCode } 139 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) |
140 return loadStoreBaseWork(name, Name, False, True, False, False, 141 codeBlobs, memFlags, instFlags, False, False, 142 'Swap', 'Swap') 143 144 def memClassName(base, post, add, writeback, \ 145 size=4, sign=False, user=False): 146 Name = base 147 148 if post: 149 Name += '_PY' 150 else: 151 Name += '_PN' 152 153 if add: 154 Name += '_AY' 155 else: 156 Name += '_AN' 157 158 if writeback: 159 Name += '_WY' 160 else: 161 Name += '_WN' 162 163 Name += ('_SZ%d' % size) 164 165 if sign: 166 Name += '_SY' 167 else: 168 Name += '_SN' 169 170 if user: 171 Name += '_UY' 172 else: 173 Name += '_UN' 174 175 return Name 176 177 def buildMemSuffix(sign, size): 178 if size == 4: 179 memSuffix = '' 180 elif size == 2: 181 if sign: 182 memSuffix = '.sh' 183 else: 184 memSuffix = '.uh' 185 elif size == 1: 186 if sign: 187 memSuffix = '.sb' 188 else: 189 memSuffix = '.ub' 190 else: 191 raise Exception, "Unrecognized size for load %d" % size 192 193 return memSuffix 194 195 def buildMemBase(base, post, writeback): 196 if post and writeback: 197 base = "MemoryPostIndex<%s>" % base 198 elif not post and writeback: 199 base = "MemoryPreIndex<%s>" % base 200 elif not post and not writeback: 201 base = "MemoryOffset<%s>" % base 202 else: 203 raise Exception, "Illegal combination of post and writeback" 204 return base 205}}; 206
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