1// -*- mode:c++ -*-
2
| 1// -*- mode:c++ -*-
2
|
3// Copyright (c) 2010 ARM Limited
| 3// Copyright (c) 2010-2012 ARM Limited
|
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 class LoadStoreInst(object):
43 def __init__(self):
44 self.fullExecTemplate = eval(self.execBase + 'Execute')
45 self.initiateAccTemplate = eval(self.execBase + 'InitiateAcc')
46 self.completeAccTemplate = eval(self.execBase + 'CompleteAcc')
47 self.declareTemplate = eval(self.decConstBase + 'Declare')
48 self.constructTemplate = eval(self.decConstBase + 'Constructor')
49
50 def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
| 4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 class LoadStoreInst(object):
43 def __init__(self):
44 self.fullExecTemplate = eval(self.execBase + 'Execute')
45 self.initiateAccTemplate = eval(self.execBase + 'InitiateAcc')
46 self.completeAccTemplate = eval(self.execBase + 'CompleteAcc')
47 self.declareTemplate = eval(self.decConstBase + 'Declare')
48 self.constructTemplate = eval(self.decConstBase + 'Constructor')
49
50 def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
|
51 base = 'Memory', wbDecl = None, pcDecl = None,
52 rasPop = False):
| 51 base='Memory', wbDecl=None, pcDecl=None,
52 rasPop=False, size=4, sign=False, faCode=None):
|
53 # Make sure flags are in lists (convert to lists if not).
54 memFlags = makeList(memFlags)
55 instFlags = makeList(instFlags)
56
57 eaCode = codeBlobs["ea_code"]
58
59 # This shouldn't be part of the eaCode, but until the exec templates
60 # are converted over it's the easiest place to put it.
61 eaCode += '\n unsigned memAccessFlags = '
62 eaCode += (string.join(memFlags, '|') + ';')
63
64 codeBlobs["ea_code"] = eaCode
65
| 53 # Make sure flags are in lists (convert to lists if not).
54 memFlags = makeList(memFlags)
55 instFlags = makeList(instFlags)
56
57 eaCode = codeBlobs["ea_code"]
58
59 # This shouldn't be part of the eaCode, but until the exec templates
60 # are converted over it's the easiest place to put it.
61 eaCode += '\n unsigned memAccessFlags = '
62 eaCode += (string.join(memFlags, '|') + ';')
63
64 codeBlobs["ea_code"] = eaCode
65
|
| 66 if faCode:
67 # For AArch64 the fa_code snippet comes already assembled here
68 codeBlobs["fa_code"] = faCode
69 elif wbDecl == None:
70 codeBlobs["fa_code"] = '''
71 if (dest != INTREG_PC) {
72 fault->annotate(ArmFault::SAS, %s);
73 fault->annotate(ArmFault::SSE, %s);
74 fault->annotate(ArmFault::SRT, dest);
75 }
76 ''' %("0" if size == 1 else
77 "1" if size == 2 else "2",
78 "true" if sign else "false")
79 else:
80 codeBlobs["fa_code"] = ''
81
|
66 macroName = Name
67 instFlagsCopy = list(instFlags)
68 codeBlobsCopy = dict(codeBlobs)
69
70 use_uops = 0
71 if wbDecl is not None or pcDecl is not None:
72 instFlagsCopy.append('IsMicroop')
73 Name = Name + 'Acc'
74 use_uops = 1
75
76 use_wb = 0
77 use_pc = 0
78 if wbDecl is not None:
79 use_wb = 1
80 if pcDecl is not None:
81 use_pc = 1
82
83 codeBlobsCopy['acc_name'] = Name
84 codeBlobsCopy['wb_decl'] = wbDecl
85 codeBlobsCopy['pc_decl'] = pcDecl
86 codeBlobsCopy['use_uops'] = 0
87 codeBlobsCopy['use_wb'] = 0
88 codeBlobsCopy['use_pc'] = 0
89 is_ras_pop = "0"
90 if rasPop:
91 is_ras_pop = "1"
92 codeBlobsCopy['is_ras_pop'] = is_ras_pop
93
94 iop = InstObjParams(name, Name, base,
95 codeBlobsCopy, instFlagsCopy)
96
97 header_output = self.declareTemplate.subst(iop)
98 decoder_output = self.constructTemplate.subst(iop)
99 exec_output = self.fullExecTemplate.subst(iop) + \
100 self.initiateAccTemplate.subst(iop) + \
101 self.completeAccTemplate.subst(iop)
102
103 if wbDecl is not None or pcDecl is not None:
104 iop = InstObjParams(name, macroName, base,
105 { "wb_decl" : wbDecl,
106 "pc_decl" : pcDecl,
107 "acc_name" : Name,
108 "use_uops" : use_uops,
109 "use_pc" : use_pc,
110 "use_wb" : use_wb,
| 82 macroName = Name
83 instFlagsCopy = list(instFlags)
84 codeBlobsCopy = dict(codeBlobs)
85
86 use_uops = 0
87 if wbDecl is not None or pcDecl is not None:
88 instFlagsCopy.append('IsMicroop')
89 Name = Name + 'Acc'
90 use_uops = 1
91
92 use_wb = 0
93 use_pc = 0
94 if wbDecl is not None:
95 use_wb = 1
96 if pcDecl is not None:
97 use_pc = 1
98
99 codeBlobsCopy['acc_name'] = Name
100 codeBlobsCopy['wb_decl'] = wbDecl
101 codeBlobsCopy['pc_decl'] = pcDecl
102 codeBlobsCopy['use_uops'] = 0
103 codeBlobsCopy['use_wb'] = 0
104 codeBlobsCopy['use_pc'] = 0
105 is_ras_pop = "0"
106 if rasPop:
107 is_ras_pop = "1"
108 codeBlobsCopy['is_ras_pop'] = is_ras_pop
109
110 iop = InstObjParams(name, Name, base,
111 codeBlobsCopy, instFlagsCopy)
112
113 header_output = self.declareTemplate.subst(iop)
114 decoder_output = self.constructTemplate.subst(iop)
115 exec_output = self.fullExecTemplate.subst(iop) + \
116 self.initiateAccTemplate.subst(iop) + \
117 self.completeAccTemplate.subst(iop)
118
119 if wbDecl is not None or pcDecl is not None:
120 iop = InstObjParams(name, macroName, base,
121 { "wb_decl" : wbDecl,
122 "pc_decl" : pcDecl,
123 "acc_name" : Name,
124 "use_uops" : use_uops,
125 "use_pc" : use_pc,
126 "use_wb" : use_wb,
|
| 127 "fa_code" : '',
|
111 "is_ras_pop" : is_ras_pop },
112 ['IsMacroop'])
113 header_output += self.declareTemplate.subst(iop)
114 decoder_output += self.constructTemplate.subst(iop)
115 exec_output += PanicExecute.subst(iop) + \
116 PanicInitiateAcc.subst(iop) + \
117 PanicCompleteAcc.subst(iop)
118
119 return (header_output, decoder_output, exec_output)
120
121 def pickPredicate(blobs):
122 opt_nz = True
123 opt_c = 'opt'
124 opt_v = True
125
126 if not isinstance(blobs, dict):
127 vals = [blobs]
128 else:
129 vals = blobs.values()
130 for val in vals:
131 if re.search('(?<!Opt)CondCodesNZ(?!.*=)', val):
132 opt_nz = False
133 if re.search('OptShiftRmCondCodesC(?!.*=)', val):
134 opt_c = 'opt_shift_rm'
135 elif re.search('(?<!Opt)CondCodesC(?!.*=)', val):
136 opt_c = 'none'
137 if re.search('(?<!Opt)CondCodesV(?!.*=)', val):
138 opt_v = False
139
140 # Build up the predicate piece by piece depending on which
141 # flags the instruction needs
142 predicate = 'testPredicate('
143 if opt_nz:
144 predicate += 'OptCondCodesNZ, '
145 else:
146 predicate += 'CondCodesNZ, '
147 if opt_c == 'opt':
148 predicate += 'OptCondCodesC, '
149 elif opt_c == 'opt_shift_rm':
150 predicate += 'OptShiftRmCondCodesC, '
151 else:
152 predicate += 'CondCodesC, '
153 if opt_v:
154 predicate += 'OptCondCodesV, '
155 else:
156 predicate += 'CondCodesV, '
157 predicate += 'condCode)'
158 predicate += '/*auto*/'
159 return predicate
160
161 def memClassName(base, post, add, writeback, \
162 size=4, sign=False, user=False):
163 Name = base
164
165 parts = { "P" : post, "A" : add, "W" : writeback,
166 "S" : sign, "U" : user }
167
168 for (letter, val) in parts.items():
169 if val:
170 Name += "_%sY" % letter
171 else:
172 Name += "_%sN" % letter
173
174 Name += ('_SZ%d' % size)
175
176 return Name
177
178 def buildMemSuffix(sign, size):
| 128 "is_ras_pop" : is_ras_pop },
129 ['IsMacroop'])
130 header_output += self.declareTemplate.subst(iop)
131 decoder_output += self.constructTemplate.subst(iop)
132 exec_output += PanicExecute.subst(iop) + \
133 PanicInitiateAcc.subst(iop) + \
134 PanicCompleteAcc.subst(iop)
135
136 return (header_output, decoder_output, exec_output)
137
138 def pickPredicate(blobs):
139 opt_nz = True
140 opt_c = 'opt'
141 opt_v = True
142
143 if not isinstance(blobs, dict):
144 vals = [blobs]
145 else:
146 vals = blobs.values()
147 for val in vals:
148 if re.search('(?<!Opt)CondCodesNZ(?!.*=)', val):
149 opt_nz = False
150 if re.search('OptShiftRmCondCodesC(?!.*=)', val):
151 opt_c = 'opt_shift_rm'
152 elif re.search('(?<!Opt)CondCodesC(?!.*=)', val):
153 opt_c = 'none'
154 if re.search('(?<!Opt)CondCodesV(?!.*=)', val):
155 opt_v = False
156
157 # Build up the predicate piece by piece depending on which
158 # flags the instruction needs
159 predicate = 'testPredicate('
160 if opt_nz:
161 predicate += 'OptCondCodesNZ, '
162 else:
163 predicate += 'CondCodesNZ, '
164 if opt_c == 'opt':
165 predicate += 'OptCondCodesC, '
166 elif opt_c == 'opt_shift_rm':
167 predicate += 'OptShiftRmCondCodesC, '
168 else:
169 predicate += 'CondCodesC, '
170 if opt_v:
171 predicate += 'OptCondCodesV, '
172 else:
173 predicate += 'CondCodesV, '
174 predicate += 'condCode)'
175 predicate += '/*auto*/'
176 return predicate
177
178 def memClassName(base, post, add, writeback, \
179 size=4, sign=False, user=False):
180 Name = base
181
182 parts = { "P" : post, "A" : add, "W" : writeback,
183 "S" : sign, "U" : user }
184
185 for (letter, val) in parts.items():
186 if val:
187 Name += "_%sY" % letter
188 else:
189 Name += "_%sN" % letter
190
191 Name += ('_SZ%d' % size)
192
193 return Name
194
195 def buildMemSuffix(sign, size):
|
179 if size == 4:
180 memSuffix = ''
| 196 if size == 8:
197 memSuffix = '_ud'
198 elif size == 4:
199 if sign:
200 memSuffix = '_sw'
201 else:
202 memSuffix = '_uw'
|
181 elif size == 2:
182 if sign:
183 memSuffix = '_sh'
184 else:
185 memSuffix = '_uh'
186 elif size == 1:
187 if sign:
188 memSuffix = '_sb'
189 else:
190 memSuffix = '_ub'
191 else:
192 raise Exception, "Unrecognized size for access %d" % size
193
194 return memSuffix
195
196 def buildMemBase(base, post, writeback):
197 if post and writeback:
198 base = "MemoryPostIndex<%s>" % base
199 elif not post and writeback:
200 base = "MemoryPreIndex<%s>" % base
201 elif not post and not writeback:
202 base = "MemoryOffset<%s>" % base
203 else:
204 raise Exception, "Illegal combination of post and writeback"
205 return base
206}};
207
| 203 elif size == 2:
204 if sign:
205 memSuffix = '_sh'
206 else:
207 memSuffix = '_uh'
208 elif size == 1:
209 if sign:
210 memSuffix = '_sb'
211 else:
212 memSuffix = '_ub'
213 else:
214 raise Exception, "Unrecognized size for access %d" % size
215
216 return memSuffix
217
218 def buildMemBase(base, post, writeback):
219 if post and writeback:
220 base = "MemoryPostIndex<%s>" % base
221 elif not post and writeback:
222 base = "MemoryPreIndex<%s>" % base
223 elif not post and not writeback:
224 base = "MemoryOffset<%s>" % base
225 else:
226 raise Exception, "Illegal combination of post and writeback"
227 return base
228}};
229
|