1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
|
41 def loadStoreBaseWork(name, Name, imm, swp, rfe, codeBlobs, memFlags,
42 instFlags, double, strex, base = 'Memory',
43 execTemplateBase = ''):
| 41 def loadStoreBaseWork(name, Name, imm, swp, rfe, srs, codeBlobs,
42 memFlags, instFlags, double, strex,
43 base = 'Memory', execTemplateBase = ''):
|
44 # Make sure flags are in lists (convert to lists if not).
45 memFlags = makeList(memFlags)
46 instFlags = makeList(instFlags)
47
48 eaCode = codeBlobs["ea_code"]
49
50 # This shouldn't be part of the eaCode, but until the exec templates
51 # are converted over it's the easiest place to put it.
52 eaCode += '\n unsigned memAccessFlags = '
53 eaCode += (string.join(memFlags, '|') + ';')
54
55 codeBlobs["ea_code"] = eaCode
56
57 iop = InstObjParams(name, Name, base, codeBlobs, instFlags)
58
59 fullExecTemplate = eval(execTemplateBase + 'Execute')
60 initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc')
61 completeAccTemplate = eval(execTemplateBase + 'CompleteAcc')
62
63 if swp:
64 declareTemplate = SwapDeclare
65 constructTemplate = SwapConstructor
66 elif rfe:
67 declareTemplate = RfeDeclare
68 constructTemplate = RfeConstructor
| 44 # Make sure flags are in lists (convert to lists if not).
45 memFlags = makeList(memFlags)
46 instFlags = makeList(instFlags)
47
48 eaCode = codeBlobs["ea_code"]
49
50 # This shouldn't be part of the eaCode, but until the exec templates
51 # are converted over it's the easiest place to put it.
52 eaCode += '\n unsigned memAccessFlags = '
53 eaCode += (string.join(memFlags, '|') + ';')
54
55 codeBlobs["ea_code"] = eaCode
56
57 iop = InstObjParams(name, Name, base, codeBlobs, instFlags)
58
59 fullExecTemplate = eval(execTemplateBase + 'Execute')
60 initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc')
61 completeAccTemplate = eval(execTemplateBase + 'CompleteAcc')
62
63 if swp:
64 declareTemplate = SwapDeclare
65 constructTemplate = SwapConstructor
66 elif rfe:
67 declareTemplate = RfeDeclare
68 constructTemplate = RfeConstructor
|
| 69 elif srs:
70 declareTemplate = SrsDeclare
71 constructTemplate = SrsConstructor
|
69 elif imm:
70 if double:
71 declareTemplate = LoadStoreDImmDeclare
72 constructTemplate = LoadStoreDImmConstructor
73 if strex:
74 declareTemplate = StoreExDImmDeclare
75 constructTemplate = StoreExDImmConstructor
76 elif strex:
77 declareTemplate = StoreExImmDeclare
78 constructTemplate = StoreExImmConstructor
79 else:
80 declareTemplate = LoadStoreImmDeclare
81 constructTemplate = LoadStoreImmConstructor
82 else:
83 if double:
84 declareTemplate = LoadStoreDRegDeclare
85 constructTemplate = LoadStoreDRegConstructor
86 else:
87 declareTemplate = LoadStoreRegDeclare
88 constructTemplate = LoadStoreRegConstructor
89
90 # (header_output, decoder_output, decode_block, exec_output)
91 return (declareTemplate.subst(iop),
92 constructTemplate.subst(iop),
93 fullExecTemplate.subst(iop)
94 + initiateAccTemplate.subst(iop)
95 + completeAccTemplate.subst(iop))
96
97 def loadStoreBase(name, Name, imm, eaCode, accCode, postAccCode,
98 memFlags, instFlags, double, strex, base = 'Memory',
99 execTemplateBase = ''):
100 codeBlobs = { "ea_code": eaCode,
101 "memacc_code": accCode,
102 "postacc_code": postAccCode,
103 "predicate_test": predicateTest }
| 72 elif imm:
73 if double:
74 declareTemplate = LoadStoreDImmDeclare
75 constructTemplate = LoadStoreDImmConstructor
76 if strex:
77 declareTemplate = StoreExDImmDeclare
78 constructTemplate = StoreExDImmConstructor
79 elif strex:
80 declareTemplate = StoreExImmDeclare
81 constructTemplate = StoreExImmConstructor
82 else:
83 declareTemplate = LoadStoreImmDeclare
84 constructTemplate = LoadStoreImmConstructor
85 else:
86 if double:
87 declareTemplate = LoadStoreDRegDeclare
88 constructTemplate = LoadStoreDRegConstructor
89 else:
90 declareTemplate = LoadStoreRegDeclare
91 constructTemplate = LoadStoreRegConstructor
92
93 # (header_output, decoder_output, decode_block, exec_output)
94 return (declareTemplate.subst(iop),
95 constructTemplate.subst(iop),
96 fullExecTemplate.subst(iop)
97 + initiateAccTemplate.subst(iop)
98 + completeAccTemplate.subst(iop))
99
100 def loadStoreBase(name, Name, imm, eaCode, accCode, postAccCode,
101 memFlags, instFlags, double, strex, base = 'Memory',
102 execTemplateBase = ''):
103 codeBlobs = { "ea_code": eaCode,
104 "memacc_code": accCode,
105 "postacc_code": postAccCode,
106 "predicate_test": predicateTest }
|
104 return loadStoreBaseWork(name, Name, imm, False, False, codeBlobs,
105 memFlags, instFlags, double, strex, base,
106 execTemplateBase)
| 107 return loadStoreBaseWork(name, Name, imm, False, False, False,
108 codeBlobs, memFlags, instFlags, double,
109 strex, base, execTemplateBase)
|
107
108 def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
109 codeBlobs = { "ea_code": eaCode,
110 "memacc_code": accCode,
111 "predicate_test": predicateTest }
| 110
111 def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
112 codeBlobs = { "ea_code": eaCode,
113 "memacc_code": accCode,
114 "predicate_test": predicateTest }
|
112 return loadStoreBaseWork(name, Name, False, False, True, codeBlobs,
113 memFlags, instFlags, False, False,
| 115 return loadStoreBaseWork(name, Name, False, False, True, False,
116 codeBlobs, memFlags, instFlags, False, False,
|
114 'RfeOp', 'Load')
115
| 117 'RfeOp', 'Load')
118
|
| 119 def SrsBase(name, Name, eaCode, accCode, memFlags, instFlags):
120 codeBlobs = { "ea_code": eaCode,
121 "memacc_code": accCode,
122 "postacc_code": "",
123 "predicate_test": predicateTest }
124 return loadStoreBaseWork(name, Name, False, False, False, True,
125 codeBlobs, memFlags, instFlags, False, False,
126 'SrsOp', 'Store')
127
|
116 def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
117 instFlags):
118 codeBlobs = { "ea_code": eaCode,
119 "preacc_code": preAccCode,
120 "postacc_code": postAccCode,
121 "predicate_test": predicateTest }
| 128 def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
129 instFlags):
130 codeBlobs = { "ea_code": eaCode,
131 "preacc_code": preAccCode,
132 "postacc_code": postAccCode,
133 "predicate_test": predicateTest }
|
122 return loadStoreBaseWork(name, Name, False, True, False, codeBlobs,
123 memFlags, instFlags, False, False,
| 134 return loadStoreBaseWork(name, Name, False, True, False, False,
135 codeBlobs, memFlags, instFlags, False, False,
|
124 'Swap', 'Swap')
125
126 def memClassName(base, post, add, writeback, \
127 size=4, sign=False, user=False):
128 Name = base
129
130 if post:
131 Name += '_PY'
132 else:
133 Name += '_PN'
134
135 if add:
136 Name += '_AY'
137 else:
138 Name += '_AN'
139
140 if writeback:
141 Name += '_WY'
142 else:
143 Name += '_WN'
144
145 Name += ('_SZ%d' % size)
146
147 if sign:
148 Name += '_SY'
149 else:
150 Name += '_SN'
151
152 if user:
153 Name += '_UY'
154 else:
155 Name += '_UN'
156
157 return Name
158
159 def buildMemSuffix(sign, size):
160 if size == 4:
161 memSuffix = ''
162 elif size == 2:
163 if sign:
164 memSuffix = '.sh'
165 else:
166 memSuffix = '.uh'
167 elif size == 1:
168 if sign:
169 memSuffix = '.sb'
170 else:
171 memSuffix = '.ub'
172 else:
173 raise Exception, "Unrecognized size for load %d" % size
174
175 return memSuffix
176
177 def buildMemBase(base, post, writeback):
178 if post and writeback:
179 base = "MemoryPostIndex<%s>" % base
180 elif not post and writeback:
181 base = "MemoryPreIndex<%s>" % base
182 elif not post and not writeback:
183 base = "MemoryOffset<%s>" % base
184 else:
185 raise Exception, "Illegal combination of post and writeback"
186 return base
187}};
188
| 136 'Swap', 'Swap')
137
138 def memClassName(base, post, add, writeback, \
139 size=4, sign=False, user=False):
140 Name = base
141
142 if post:
143 Name += '_PY'
144 else:
145 Name += '_PN'
146
147 if add:
148 Name += '_AY'
149 else:
150 Name += '_AN'
151
152 if writeback:
153 Name += '_WY'
154 else:
155 Name += '_WN'
156
157 Name += ('_SZ%d' % size)
158
159 if sign:
160 Name += '_SY'
161 else:
162 Name += '_SN'
163
164 if user:
165 Name += '_UY'
166 else:
167 Name += '_UN'
168
169 return Name
170
171 def buildMemSuffix(sign, size):
172 if size == 4:
173 memSuffix = ''
174 elif size == 2:
175 if sign:
176 memSuffix = '.sh'
177 else:
178 memSuffix = '.uh'
179 elif size == 1:
180 if sign:
181 memSuffix = '.sb'
182 else:
183 memSuffix = '.ub'
184 else:
185 raise Exception, "Unrecognized size for load %d" % size
186
187 return memSuffix
188
189 def buildMemBase(base, post, writeback):
190 if post and writeback:
191 base = "MemoryPostIndex<%s>" % base
192 elif not post and writeback:
193 base = "MemoryPreIndex<%s>" % base
194 elif not post and not writeback:
195 base = "MemoryOffset<%s>" % base
196 else:
197 raise Exception, "Illegal combination of post and writeback"
198 return base
199}};
200
|