1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41 def loadStoreBaseWork(name, Name, imm, swp, rfe, codeBlobs, memFlags,
42 instFlags, double, base = 'Memory',
43 execTemplateBase = ''):
44 # Make sure flags are in lists (convert to lists if not).
45 memFlags = makeList(memFlags)
46 instFlags = makeList(instFlags)
47
48 eaCode = codeBlobs["ea_code"]
49
50 # This shouldn't be part of the eaCode, but until the exec templates
51 # are converted over it's the easiest place to put it.
52 eaCode += '\n unsigned memAccessFlags = '
53 eaCode += (string.join(memFlags, '|') + ';')
54
55 codeBlobs["ea_code"] = eaCode
56
57 iop = InstObjParams(name, Name, base, codeBlobs, instFlags)
58
59 fullExecTemplate = eval(execTemplateBase + 'Execute')
60 initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc')
61 completeAccTemplate = eval(execTemplateBase + 'CompleteAcc')
62
63 if swp:
64 declareTemplate = SwapDeclare
65 constructTemplate = SwapConstructor
66 elif rfe:
67 declareTemplate = RfeDeclare
68 constructTemplate = RfeConstructor
69 elif imm:
70 if double:
71 declareTemplate = LoadStoreDImmDeclare
72 constructTemplate = LoadStoreDImmConstructor
73 else:
74 declareTemplate = LoadStoreImmDeclare
75 constructTemplate = LoadStoreImmConstructor
76 else:
77 if double:
78 declareTemplate = LoadStoreDRegDeclare
79 constructTemplate = LoadStoreDRegConstructor
80 else:
81 declareTemplate = LoadStoreRegDeclare
82 constructTemplate = LoadStoreRegConstructor
83
84 # (header_output, decoder_output, decode_block, exec_output)
85 return (declareTemplate.subst(iop),
86 constructTemplate.subst(iop),
87 fullExecTemplate.subst(iop)
88 + initiateAccTemplate.subst(iop)
89 + completeAccTemplate.subst(iop))
90
91 def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags,
92 instFlags, double, base = 'Memory',
93 execTemplateBase = ''):
94 codeBlobs = { "ea_code": eaCode,
95 "memacc_code": accCode,
96 "predicate_test": predicateTest }
97 return loadStoreBaseWork(name, Name, imm, False, False, codeBlobs,
98 memFlags, instFlags, double, base,
99 execTemplateBase)
100
101 def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
102 codeBlobs = { "ea_code": eaCode,
103 "memacc_code": accCode,
104 "predicate_test": predicateTest }
105 return loadStoreBaseWork(name, Name, False, False, True, codeBlobs,
106 memFlags, instFlags, False, 'RfeOp', 'Load')
107
108 def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
109 instFlags):
110 codeBlobs = { "ea_code": eaCode,
111 "preacc_code": preAccCode,
112 "postacc_code": postAccCode,
113 "predicate_test": predicateTest }
114 return loadStoreBaseWork(name, Name, False, True, False, codeBlobs,
115 memFlags, instFlags, False, 'Swap', 'Swap')
116
117 def memClassName(base, post, add, writeback, \
118 size=4, sign=False, user=False):
119 Name = base
120
121 if post:
122 Name += '_PY'
123 else:
124 Name += '_PN'
125
126 if add:
127 Name += '_AY'
128 else:
129 Name += '_AN'
130
131 if writeback:
132 Name += '_WY'
133 else:
134 Name += '_WN'
135
136 Name += ('_SZ%d' % size)
137
138 if sign:
139 Name += '_SY'
140 else:
141 Name += '_SN'
142
143 if user:
144 Name += '_UY'
145 else:
146 Name += '_UN'
147
148 return Name
149
150 def buildMemSuffix(sign, size):
151 if size == 4:
152 memSuffix = ''
153 elif size == 2:
154 if sign:
155 memSuffix = '.sh'
156 else:
157 memSuffix = '.uh'
158 elif size == 1:
159 if sign:
160 memSuffix = '.sb'
161 else:
162 memSuffix = '.ub'
163 else:
164 raise Exception, "Unrecognized size for load %d" % size
165
166 return memSuffix
167
168 def buildMemBase(base, post, writeback):
169 if post and writeback:
170 base = "MemoryPostIndex<%s>" % base
171 elif not post and writeback:
172 base = "MemoryPreIndex<%s>" % base
173 elif not post and not writeback:
174 base = "MemoryOffset<%s>" % base
175 else:
176 raise Exception, "Illegal combination of post and writeback"
177 return base
178}};
179