ldr64.isa (12856:cca88f84cb80) ldr64.isa (13367:dc06baae4275)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2014, 2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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69 self.memFlags.append("ArmISA::TLB::UserMode")
70
71 if self.flavor == "dprefetch":
72 self.memFlags.append("Request::PREFETCH")
73 self.instFlags = ['IsDataPrefetch']
74 elif self.flavor == "iprefetch":
75 self.memFlags.append("Request::PREFETCH")
76 self.instFlags = ['IsInstPrefetch']
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2014, 2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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69 self.memFlags.append("ArmISA::TLB::UserMode")
70
71 if self.flavor == "dprefetch":
72 self.memFlags.append("Request::PREFETCH")
73 self.instFlags = ['IsDataPrefetch']
74 elif self.flavor == "iprefetch":
75 self.memFlags.append("Request::PREFETCH")
76 self.instFlags = ['IsInstPrefetch']
77 elif self.flavor == "mprefetch":
78 self.memFlags.append("((((dest>>3)&3)==2)? \
79 (Request::PF_EXCLUSIVE):(Request::PREFETCH))")
80 self.instFlags = ['IsDataPrefetch']
77 if self.micro:
78 self.instFlags.append("IsMicroop")
79
80 if self.flavor in ("acexp", "exp"):
81 # For exclusive pair ops alignment check is based on total size
82 self.memFlags.append("%d" % int(math.log(self.size, 2) + 1))
83 elif not (self.size == 16 and self.top):
84 # Only the first microop should perform alignment checking.

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171 super(LoadRawRegInst64, self).__init__(*args, **kargs)
172 self.offset = ""
173
174 class LoadSingle64(LoadInst64):
175 def emit(self):
176 self.buildEACode()
177
178 # Code that actually handles the access
81 if self.micro:
82 self.instFlags.append("IsMicroop")
83
84 if self.flavor in ("acexp", "exp"):
85 # For exclusive pair ops alignment check is based on total size
86 self.memFlags.append("%d" % int(math.log(self.size, 2) + 1))
87 elif not (self.size == 16 and self.top):
88 # Only the first microop should perform alignment checking.

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175 super(LoadRawRegInst64, self).__init__(*args, **kargs)
176 self.offset = ""
177
178 class LoadSingle64(LoadInst64):
179 def emit(self):
180 self.buildEACode()
181
182 # Code that actually handles the access
179 if self.flavor in ("dprefetch", "iprefetch"):
183 if self.flavor in ("dprefetch", "iprefetch", "mprefetch"):
180 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
181 elif self.flavor == "fp":
182 if self.size in (1, 2, 4):
183 accCode = '''
184 AA64FpDestP0_uw = cSwap(Mem%s,
185 isBigEndian64(xc->tcBase()));
186 AA64FpDestP1_uw = 0;
187 AA64FpDestP2_uw = 0;

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360 buildLoads64("ldrsw", "LDRSW64", 4, True, flavor="widen")
361 buildLoads64("ldr", "LDRW64", 4, False)
362 buildLoads64("ldr", "LDRX64", 8, False)
363 buildLoads64("ldr", "LDRBFP64", 1, False, flavor="fp")
364 buildLoads64("ldr", "LDRHFP64", 2, False, flavor="fp")
365 buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp")
366 buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp")
367
184 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
185 elif self.flavor == "fp":
186 if self.size in (1, 2, 4):
187 accCode = '''
188 AA64FpDestP0_uw = cSwap(Mem%s,
189 isBigEndian64(xc->tcBase()));
190 AA64FpDestP1_uw = 0;
191 AA64FpDestP2_uw = 0;

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364 buildLoads64("ldrsw", "LDRSW64", 4, True, flavor="widen")
365 buildLoads64("ldr", "LDRW64", 4, False)
366 buildLoads64("ldr", "LDRX64", 8, False)
367 buildLoads64("ldr", "LDRBFP64", 1, False, flavor="fp")
368 buildLoads64("ldr", "LDRHFP64", 2, False, flavor="fp")
369 buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp")
370 buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp")
371
368 LoadImm64("prfm", "PRFM64_IMM", 8, flavor="dprefetch").emit()
369 LoadReg64("prfm", "PRFM64_REG", 8, flavor="dprefetch").emit()
370 LoadLit64("prfm", "PRFM64_LIT", 8, literal=True, flavor="dprefetch").emit()
371 LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="dprefetch").emit()
372 LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit()
373 LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit()
374 LoadLit64("prfm", "PRFM64_LIT", 8, literal=True,
375 flavor="mprefetch").emit()
376 LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit()
372
373 LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit()
374 LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit()
375 LoadImm64("ldursb", "LDURSBX64_IMM", 1, True, flavor="widen").emit()
376 LoadImm64("ldurh", "LDURH64_IMM", 2, False).emit()
377 LoadImm64("ldursh", "LDURSHW64_IMM", 2, True).emit()
378 LoadImm64("ldursh", "LDURSHX64_IMM", 2, True, flavor="widen").emit()
379 LoadImm64("ldursw", "LDURSW64_IMM", 4, True, flavor="widen").emit()

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378 LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit()
379 LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit()
380 LoadImm64("ldursb", "LDURSBX64_IMM", 1, True, flavor="widen").emit()
381 LoadImm64("ldurh", "LDURH64_IMM", 2, False).emit()
382 LoadImm64("ldursh", "LDURSHW64_IMM", 2, True).emit()
383 LoadImm64("ldursh", "LDURSHX64_IMM", 2, True, flavor="widen").emit()
384 LoadImm64("ldursw", "LDURSW64_IMM", 4, True, flavor="widen").emit()

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