ldr.isa (8588:ef28ed90449d) ldr.isa (10037:5cac77888310)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
3// Copyright (c) 2010-2011 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 21 unchanged lines hidden (view full) ---

33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 21 unchanged lines hidden (view full) ---

33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41 import math
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 class LoadInst(LoadStoreInst):
47 execBase = 'Load'
48

--- 24 unchanged lines hidden (view full) ---

73 global header_output, decoder_output, exec_output
74
75 codeBlobs = self.codeBlobs
76 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
77 (newHeader,
78 newDecoder,
79 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
80 self.memFlags, instFlags, base,
42
43 header_output = ""
44 decoder_output = ""
45 exec_output = ""
46
47 class LoadInst(LoadStoreInst):
48 execBase = 'Load'
49

--- 24 unchanged lines hidden (view full) ---

74 global header_output, decoder_output, exec_output
75
76 codeBlobs = self.codeBlobs
77 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
78 (newHeader,
79 newDecoder,
80 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
81 self.memFlags, instFlags, base,
81 wbDecl, pcDecl, self.rasPop)
82 wbDecl, pcDecl, self.rasPop,
83 self.size, self.sign)
82
83 header_output += newHeader
84 decoder_output += newDecoder
85 exec_output += newExec
86
87 class RfeInst(LoadInst):
88 decConstBase = 'Rfe'
89

--- 65 unchanged lines hidden (view full) ---

155 def __init__(self, *args, **kargs):
156 super(LoadSingle, self).__init__(*args, **kargs)
157
158 # Build the default class name
159 self.Name = self.nameFunc(self.post, self.add, self.writeback,
160 self.size, self.sign, self.user)
161
162 # Add memory request flags where necessary
84
85 header_output += newHeader
86 decoder_output += newDecoder
87 exec_output += newExec
88
89 class RfeInst(LoadInst):
90 decConstBase = 'Rfe'
91

--- 65 unchanged lines hidden (view full) ---

157 def __init__(self, *args, **kargs):
158 super(LoadSingle, self).__init__(*args, **kargs)
159
160 # Build the default class name
161 self.Name = self.nameFunc(self.post, self.add, self.writeback,
162 self.size, self.sign, self.user)
163
164 # Add memory request flags where necessary
163 self.memFlags.append("%d" % (self.size - 1))
165 self.memFlags.append("%d" % int(math.log(self.size, 2)))
164 if self.user:
165 self.memFlags.append("ArmISA::TLB::UserMode")
166
167 self.instFlags = []
168 if self.flavor == "dprefetch":
169 self.memFlags.append("Request::PREFETCH")
170 self.instFlags = ['IsDataPrefetch']
171 elif self.flavor == "iprefetch":

--- 199 unchanged lines hidden --- 		166 if self.user:
167 self.memFlags.append("ArmISA::TLB::UserMode")
168
169 self.instFlags = []
170 if self.flavor == "dprefetch":
171 self.memFlags.append("Request::PREFETCH")
172 self.instFlags = ['IsDataPrefetch']
173 elif self.flavor == "iprefetch":

--- 199 unchanged lines hidden ---