ldr.isa (8303:5a95f1d2494e) ldr.isa (8304:16911ff780d3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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136 if self.add and self.post and self.writeback and not self.sign and \
137 not self.user and self.size == 4:
138 self.rasPop = True
139
140 class LoadRegInst(LoadInst):
141 def __init__(self, *args, **kargs):
142 super(LoadRegInst, self).__init__(*args, **kargs)
143 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 127 unchanged lines hidden (view full) ---

136 if self.add and self.post and self.writeback and not self.sign and \
137 not self.user and self.size == 4:
138 self.rasPop = True
139
140 class LoadRegInst(LoadInst):
141 def __init__(self, *args, **kargs):
142 super(LoadRegInst, self).__init__(*args, **kargs)
143 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
144 " shiftType, CondCodesC)"
144 " shiftType, OptShiftRmCondCodesC)"
145 if self.add:
146 self.wbDecl = '''
147 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
148 '''
149 else:
150 self.wbDecl = '''
151 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
152 '''

--- 218 unchanged lines hidden --- 		145 if self.add:
146 self.wbDecl = '''
147 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
148 '''
149 else:
150 self.wbDecl = '''
151 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
152 '''

--- 218 unchanged lines hidden ---