ldr.isa (8302:9f23d01421de) ldr.isa (8303:5a95f1d2494e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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101 offset -= 8
102 self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset
103
104 wbDiff = -8
105 if self.add:
106 wbDiff = 8
107 accCode = '''
108 CPSR cpsr = Cpsr;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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101 offset -= 8
102 self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset
103
104 wbDiff = -8
105 if self.add:
106 wbDiff = 8
107 accCode = '''
108 CPSR cpsr = Cpsr;
109 URc = cpsr | CondCodesF | CondCodesGE;
109 cpsr.nz = CondCodesNZ;
110 cpsr.c = CondCodesC;
111 cpsr.v = CondCodesV;
112 cpsr.ge = CondCodesGE;
113 URc = cpsr;
110 URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
111 URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
112 '''
113 self.codeBlobs["memacc_code"] = accCode
114
115 wbDecl = None
116 pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);"
117

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132 if self.add and self.post and self.writeback and not self.sign and \
133 not self.user and self.size == 4:
134 self.rasPop = True
135
136 class LoadRegInst(LoadInst):
137 def __init__(self, *args, **kargs):
138 super(LoadRegInst, self).__init__(*args, **kargs)
139 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
114 URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
115 URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
116 '''
117 self.codeBlobs["memacc_code"] = accCode
118
119 wbDecl = None
120 pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);"
121

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136 if self.add and self.post and self.writeback and not self.sign and \
137 not self.user and self.size == 4:
138 self.rasPop = True
139
140 class LoadRegInst(LoadInst):
141 def __init__(self, *args, **kargs):
142 super(LoadRegInst, self).__init__(*args, **kargs)
143 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
140 " shiftType, CondCodesF<29:>)"
144 " shiftType, CondCodesC)"
141 if self.add:
142 self.wbDecl = '''
143 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
144 '''
145 else:
146 self.wbDecl = '''
147 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
148 '''

--- 218 unchanged lines hidden --- 		145 if self.add:
146 self.wbDecl = '''
147 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
148 '''
149 else:
150 self.wbDecl = '''
151 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
152 '''

--- 218 unchanged lines hidden ---