ldr.isa (8203:78b9f056d58a) | ldr.isa (8301:858384f3af1c) |
---|---|
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 92 unchanged lines hidden (view full) --- 101 offset -= 8 102 self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset 103 104 wbDiff = -8 105 if self.add: 106 wbDiff = 8 107 accCode = ''' 108 CPSR cpsr = Cpsr; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 92 unchanged lines hidden (view full) --- 101 offset -= 8 102 self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset 103 104 wbDiff = -8 105 if self.add: 106 wbDiff = 8 107 accCode = ''' 108 CPSR cpsr = Cpsr; |
109 URc = cpsr | CondCodes; | 109 URc = cpsr | CondCodesF | CondCodesQ | CondCodesGE; |
110 URa = cSwap<uint32_t>(Mem.ud, cpsr.e); 111 URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 112 ''' 113 self.codeBlobs["memacc_code"] = accCode 114 115 wbDecl = None 116 pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);" 117 --- 14 unchanged lines hidden (view full) --- 132 if self.add and self.post and self.writeback and not self.sign and \ 133 not self.user and self.size == 4: 134 self.rasPop = True 135 136 class LoadRegInst(LoadInst): 137 def __init__(self, *args, **kargs): 138 super(LoadRegInst, self).__init__(*args, **kargs) 139 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ | 110 URa = cSwap<uint32_t>(Mem.ud, cpsr.e); 111 URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 112 ''' 113 self.codeBlobs["memacc_code"] = accCode 114 115 wbDecl = None 116 pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);" 117 --- 14 unchanged lines hidden (view full) --- 132 if self.add and self.post and self.writeback and not self.sign and \ 133 not self.user and self.size == 4: 134 self.rasPop = True 135 136 class LoadRegInst(LoadInst): 137 def __init__(self, *args, **kargs): 138 super(LoadRegInst, self).__init__(*args, **kargs) 139 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ |
140 " shiftType, CondCodes<29:>)" | 140 " shiftType, CondCodesF<29:>)" |
141 if self.add: 142 self.wbDecl = ''' 143 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 144 ''' 145 else: 146 self.wbDecl = ''' 147 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 148 ''' --- 218 unchanged lines hidden --- | 141 if self.add: 142 self.wbDecl = ''' 143 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 144 ''' 145 else: 146 self.wbDecl = ''' 147 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 148 ''' --- 218 unchanged lines hidden --- |