ldr.isa (8140:7449084b1612) ldr.isa (8203:78b9f056d58a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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53 self.name = mnem
54 self.post = post
55 self.add = add
56 self.writeback = writeback
57 self.size = size
58 self.sign = sign
59 self.user = user
60 self.flavor = flavor
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 44 unchanged lines hidden (view full) ---

53 self.name = mnem
54 self.post = post
55 self.add = add
56 self.writeback = writeback
57 self.size = size
58 self.sign = sign
59 self.user = user
60 self.flavor = flavor
61 self.rasPop = False
61
62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = {"postacc_code" : ""}
69
70 def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None):
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
79 self.memFlags, instFlags, base,
62
63 if self.add:
64 self.op = " +"
65 else:
66 self.op = " -"
67
68 self.memFlags = ["ArmISA::TLB::MustBeOne"]
69 self.codeBlobs = {"postacc_code" : ""}
70
71 def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None):
72
73 global header_output, decoder_output, exec_output
74
75 codeBlobs = self.codeBlobs
76 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
77 (newHeader,
78 newDecoder,
79 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
80 self.memFlags, instFlags, base,
80 wbDecl, pcDecl)
81 wbDecl, pcDecl, self.rasPop)
81
82 header_output += newHeader
83 decoder_output += newDecoder
84 exec_output += newExec
85
86 class RfeInst(LoadInst):
87 decConstBase = 'Rfe'
88

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123 super(LoadImmInst, self).__init__(*args, **kargs)
124 self.offset = self.op + " imm"
125
126 if self.add:
127 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
128 else:
129 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
130
82
83 header_output += newHeader
84 decoder_output += newDecoder
85 exec_output += newExec
86
87 class RfeInst(LoadInst):
88 decConstBase = 'Rfe'
89

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124 super(LoadImmInst, self).__init__(*args, **kargs)
125 self.offset = self.op + " imm"
126
127 if self.add:
128 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
129 else:
130 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
131
132 if self.add and self.post and self.writeback and not self.sign and \
133 not self.user and self.size == 4:
134 self.rasPop = True
135
131 class LoadRegInst(LoadInst):
132 def __init__(self, *args, **kargs):
133 super(LoadRegInst, self).__init__(*args, **kargs)
134 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
135 " shiftType, CondCodes<29:>)"
136 if self.add:
137 self.wbDecl = '''
138 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);

--- 223 unchanged lines hidden --- 		136 class LoadRegInst(LoadInst):
137 def __init__(self, *args, **kargs):
138 super(LoadRegInst, self).__init__(*args, **kargs)
139 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
140 " shiftType, CondCodes<29:>)"
141 if self.add:
142 self.wbDecl = '''
143 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);

--- 223 unchanged lines hidden ---