ldr.isa (7646:a444dbee8c07) ldr.isa (7648:3e561a5c0456)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 53 unchanged lines hidden (view full) ---

62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = {"postacc_code" : ""}
69
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 53 unchanged lines hidden (view full) ---

62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = {"postacc_code" : ""}
69
70 def emitHelper(self, base = 'Memory', wbDecl = None):
70 def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
79 self.memFlags, [], base, wbDecl)
79 self.memFlags, instFlags, base, wbDecl)
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class RfeInst(LoadInst):
86 decConstBase = 'Rfe'
87

--- 25 unchanged lines hidden (view full) ---

113 Cpsr = ~CondCodesMask & newCpsr;
114 CondCodes = CondCodesMask & newCpsr;
115 '''
116 self.codeBlobs["memacc_code"] = accCode
117
118 wbDecl = None
119 if self.writeback:
120 wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class RfeInst(LoadInst):
86 decConstBase = 'Rfe'
87

--- 25 unchanged lines hidden (view full) ---

113 Cpsr = ~CondCodesMask & newCpsr;
114 CondCodes = CondCodesMask & newCpsr;
115 '''
116 self.codeBlobs["memacc_code"] = accCode
117
118 wbDecl = None
119 if self.writeback:
120 wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
121 self.emitHelper('RfeOp', wbDecl)
121 self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"])
122
123 class LoadImmInst(LoadInst):
124 def __init__(self, *args, **kargs):
125 super(LoadImmInst, self).__init__(*args, **kargs)
126 self.offset = self.op + " imm"
127
128 if self.add:
129 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"

--- 229 unchanged lines hidden --- 		122
123 class LoadImmInst(LoadInst):
124 def __init__(self, *args, **kargs):
125 super(LoadImmInst, self).__init__(*args, **kargs)
126 self.offset = self.op + " imm"
127
128 if self.add:
129 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"

--- 229 unchanged lines hidden ---