ldr.isa (7644:62873d5c2bfc) ldr.isa (7646:a444dbee8c07)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = {"postacc_code" : ""}
69
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = {"postacc_code" : ""}
69
70 def emitHelper(self, base = 'Memory'):
70 def emitHelper(self, base = 'Memory', wbDecl = None):
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
79 self.memFlags, [], base)
79 self.memFlags, [], base, wbDecl)
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class RfeInst(LoadInst):
86 decConstBase = 'Rfe'
87

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108 NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
109 uint32_t newCpsr =
110 cpsrWriteByInstr(cpsr | CondCodes,
111 cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
112 0xF, true, sctlr.nmfi);
113 Cpsr = ~CondCodesMask & newCpsr;
114 CondCodes = CondCodesMask & newCpsr;
115 '''
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class RfeInst(LoadInst):
86 decConstBase = 'Rfe'
87

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108 NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
109 uint32_t newCpsr =
110 cpsrWriteByInstr(cpsr | CondCodes,
111 cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
112 0xF, true, sctlr.nmfi);
113 Cpsr = ~CondCodesMask & newCpsr;
114 CondCodes = CondCodesMask & newCpsr;
115 '''
116 if self.writeback:
117 accCode += "Base = Base + %s;\n" % wbDiff
118 self.codeBlobs["memacc_code"] = accCode
119
116 self.codeBlobs["memacc_code"] = accCode
117
120 self.emitHelper('RfeOp')
118 wbDecl = None
119 if self.writeback:
120 wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
121 self.emitHelper('RfeOp', wbDecl)
121
122 class LoadImmInst(LoadInst):
123 def __init__(self, *args, **kargs):
124 super(LoadImmInst, self).__init__(*args, **kargs)
125 self.offset = self.op + " imm"
126
122
123 class LoadImmInst(LoadInst):
124 def __init__(self, *args, **kargs):
125 super(LoadImmInst, self).__init__(*args, **kargs)
126 self.offset = self.op + " imm"
127
128 if self.add:
129 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
130 else:
131 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
132
127 class LoadRegInst(LoadInst):
128 def __init__(self, *args, **kargs):
129 super(LoadRegInst, self).__init__(*args, **kargs)
130 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
131 " shiftType, CondCodes<29:>)"
133 class LoadRegInst(LoadInst):
134 def __init__(self, *args, **kargs):
135 super(LoadRegInst, self).__init__(*args, **kargs)
136 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
137 " shiftType, CondCodes<29:>)"
138 if self.add:
139 self.wbDecl = '''
140 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
141 '''
142 else:
143 self.wbDecl = '''
144 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
145 '''
132
133 class LoadSingle(LoadInst):
134 def __init__(self, *args, **kargs):
135 super(LoadSingle, self).__init__(*args, **kargs)
136
137 # Build the default class name
138 self.Name = self.nameFunc(self.post, self.add, self.writeback,
139 self.size, self.sign, self.user)

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170 if self.flavor == "prefetch":
171 accCode = 'uint64_t temp = Mem%s; temp = temp;'
172 elif self.flavor == "fp":
173 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
174 else:
175 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
176 accCode = accCode % buildMemSuffix(self.sign, self.size)
177
146
147 class LoadSingle(LoadInst):
148 def __init__(self, *args, **kargs):
149 super(LoadSingle, self).__init__(*args, **kargs)
150
151 # Build the default class name
152 self.Name = self.nameFunc(self.post, self.add, self.writeback,
153 self.size, self.sign, self.user)

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184 if self.flavor == "prefetch":
185 accCode = 'uint64_t temp = Mem%s; temp = temp;'
186 elif self.flavor == "fp":
187 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
188 else:
189 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
190 accCode = accCode % buildMemSuffix(self.sign, self.size)
191
178 if self.writeback:
179 accCode += "Base = Base %s;\n" % self.offset
180
181 self.codeBlobs["memacc_code"] = accCode
182
183 # Push it out to the output files
184 base = buildMemBase(self.basePrefix, self.post, self.writeback)
192 self.codeBlobs["memacc_code"] = accCode
193
194 # Push it out to the output files
195 base = buildMemBase(self.basePrefix, self.post, self.writeback)
185 self.emitHelper(base)
196 wbDecl = None
197 if self.writeback:
198 wbDecl = self.wbDecl
199 self.emitHelper(base, wbDecl)
186
187 def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
188 return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
189
190 class LoadImm(LoadImmInst, LoadSingle):
200
201 def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
202 return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
203
204 class LoadImm(LoadImmInst, LoadSingle):
191 decConstBase = 'LoadStoreImm'
205 decConstBase = 'LoadImm'
192 basePrefix = 'MemoryImm'
193 nameFunc = staticmethod(loadImmClassName)
194
195 def loadRegClassName(post, add, writeback, size=4, sign=False, user=False):
196 return memClassName("LOAD_REG", post, add, writeback, size, sign, user)
197
198 class LoadReg(LoadRegInst, LoadSingle):
206 basePrefix = 'MemoryImm'
207 nameFunc = staticmethod(loadImmClassName)
208
209 def loadRegClassName(post, add, writeback, size=4, sign=False, user=False):
210 return memClassName("LOAD_REG", post, add, writeback, size, sign, user)
211
212 class LoadReg(LoadRegInst, LoadSingle):
199 decConstBase = 'LoadStoreReg'
213 decConstBase = 'LoadReg'
200 basePrefix = 'MemoryReg'
201 nameFunc = staticmethod(loadRegClassName)
202
203 class LoadDouble(LoadInst):
204 def __init__(self, *args, **kargs):
205 super(LoadDouble, self).__init__(*args, **kargs)
206
207 # Build the default class name

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239 '''
240 else:
241 accCode = '''
242 uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e);
243 FpDest.uw = (uint32_t)swappedMem;
244 FpDest2.uw = (uint32_t)(swappedMem >> 32);
245 '''
246
214 basePrefix = 'MemoryReg'
215 nameFunc = staticmethod(loadRegClassName)
216
217 class LoadDouble(LoadInst):
218 def __init__(self, *args, **kargs):
219 super(LoadDouble, self).__init__(*args, **kargs)
220
221 # Build the default class name

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253 '''
254 else:
255 accCode = '''
256 uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e);
257 FpDest.uw = (uint32_t)swappedMem;
258 FpDest2.uw = (uint32_t)(swappedMem >> 32);
259 '''
260
247 if self.writeback:
248 accCode += "Base = Base %s;\n" % self.offset
249
250 self.codeBlobs["memacc_code"] = accCode
251
252 # Push it out to the output files
253 base = buildMemBase(self.basePrefix, self.post, self.writeback)
261 self.codeBlobs["memacc_code"] = accCode
262
263 # Push it out to the output files
264 base = buildMemBase(self.basePrefix, self.post, self.writeback)
254 self.emitHelper(base)
265 wbDecl = None
266 if self.writeback:
267 wbDecl = self.wbDecl
268 self.emitHelper(base, wbDecl)
255
256 def loadDoubleImmClassName(post, add, writeback):
257 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
258
259 class LoadDoubleImm(LoadImmInst, LoadDouble):
260 decConstBase = 'LoadStoreDImm'
261 basePrefix = 'MemoryDImm'
262 nameFunc = staticmethod(loadDoubleImmClassName)
263
264 def loadDoubleRegClassName(post, add, writeback):
265 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
266
267 class LoadDoubleReg(LoadRegInst, LoadDouble):
269
270 def loadDoubleImmClassName(post, add, writeback):
271 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
272
273 class LoadDoubleImm(LoadImmInst, LoadDouble):
274 decConstBase = 'LoadStoreDImm'
275 basePrefix = 'MemoryDImm'
276 nameFunc = staticmethod(loadDoubleImmClassName)
277
278 def loadDoubleRegClassName(post, add, writeback):
279 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
280
281 class LoadDoubleReg(LoadRegInst, LoadDouble):
268 decConstBase = 'LoadStoreDReg'
282 decConstBase = 'LoadDReg'
269 basePrefix = 'MemoryDReg'
270 nameFunc = staticmethod(loadDoubleRegClassName)
271
272 def buildLoads(mnem, size=4, sign=False, user=False):
273 LoadImm(mnem, True, True, True, size, sign, user).emit()
274 LoadReg(mnem, True, True, True, size, sign, user).emit()
275 LoadImm(mnem, True, False, True, size, sign, user).emit()
276 LoadReg(mnem, True, False, True, size, sign, user).emit()

--- 68 unchanged lines hidden --- 		283 basePrefix = 'MemoryDReg'
284 nameFunc = staticmethod(loadDoubleRegClassName)
285
286 def buildLoads(mnem, size=4, sign=False, user=False):
287 LoadImm(mnem, True, True, True, size, sign, user).emit()
288 LoadReg(mnem, True, True, True, size, sign, user).emit()
289 LoadImm(mnem, True, False, True, size, sign, user).emit()
290 LoadReg(mnem, True, False, True, size, sign, user).emit()

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