ldr.isa (7590:27dbb92bbad5) ldr.isa (7593:aa32d1398dfd)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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201 super(LoadDouble, self).__init__(*args, **kargs)
202
203 # Build the default class name
204 self.Name = self.nameFunc(self.post, self.add, self.writeback)
205
206 # Add memory request flags where necessary
207 if self.flavor == "exclusive":
208 self.memFlags.append("Request::LLSC")
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 192 unchanged lines hidden (view full) ---

201 super(LoadDouble, self).__init__(*args, **kargs)
202
203 # Build the default class name
204 self.Name = self.nameFunc(self.post, self.add, self.writeback)
205
206 # Add memory request flags where necessary
207 if self.flavor == "exclusive":
208 self.memFlags.append("Request::LLSC")
209 self.memFlags.append("ArmISA::TLB::AlignWord")
209 self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
210 else:
211 self.memFlags.append("ArmISA::TLB::AlignWord")
210
211 # Disambiguate the class name for different flavors of loads
212 if self.flavor != "normal":
213 self.Name = "%s_%s" % (self.name.upper(), self.Name)
214
215 def emit(self):
216 # Address computation code
217 eaCode = "EA = Base"

--- 117 unchanged lines hidden ---
212
213 # Disambiguate the class name for different flavors of loads
214 if self.flavor != "normal":
215 self.Name = "%s_%s" % (self.name.upper(), self.Name)
216
217 def emit(self):
218 # Address computation code
219 eaCode = "EA = Base"

--- 117 unchanged lines hidden ---