| ldr.isa (7404:bfc74724914e) | ldr.isa (7590:27dbb92bbad5) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 29 unchanged lines hidden (view full) --- 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 29 unchanged lines hidden (view full) --- 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 |
| 46 def loadImmClassName(post, add, writeback, \ 47 size=4, sign=False, user=False): 48 return memClassName("LOAD_IMM", post, add, writeback, 49 size, sign, user) | 46 class LoadInst(LoadStoreInst): 47 execBase = 'Load' |
| 50 | 48 |
| 51 def loadRegClassName(post, add, writeback, \ 52 size=4, sign=False, user=False): 53 return memClassName("LOAD_REG", post, add, writeback, 54 size, sign, user) | 49 def __init__(self, mnem, post, add, writeback, 50 size=4, sign=False, user=False, flavor="normal"): 51 super(LoadInst, self).__init__() |
| 55 | 52 |
| 56 def loadDoubleImmClassName(post, add, writeback): 57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) | 53 self.name = mnem 54 self.post = post 55 self.add = add 56 self.writeback = writeback 57 self.size = size 58 self.sign = sign 59 self.user = user 60 self.flavor = flavor |
| 58 | 61 |
| 59 def loadDoubleRegClassName(post, add, writeback): 60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) | 62 if self.add: 63 self.op = " +" 64 else: 65 self.op = " -" |
| 61 | 66 |
| 62 def emitLoad(name, Name, imm, eaCode, accCode, \ 63 memFlags, instFlags, base, double=False): 64 global header_output, decoder_output, exec_output | 67 self.memFlags = ["ArmISA::TLB::MustBeOne"] 68 self.codeBlobs = {"postacc_code" : ""} |
| 65 | 69 |
| 66 (newHeader, 67 newDecoder, 68 newExec) = loadStoreBase(name, Name, imm, 69 eaCode, accCode, "", 70 memFlags, instFlags, double, False, 71 base, execTemplateBase = 'Load') | 70 def emitHelper(self, base = 'Memory'): |
| 72 | 71 |
| 73 header_output += newHeader 74 decoder_output += newDecoder 75 exec_output += newExec | 72 global header_output, decoder_output, exec_output |
| 76 | 73 |
| 77 def buildImmLoad(mnem, post, add, writeback, \ 78 size=4, sign=False, user=False, \ 79 prefetch=False, ldrex=False, vldr=False): 80 name = mnem 81 Name = loadImmClassName(post, add, writeback, \ 82 size, sign, user) | 74 codeBlobs = self.codeBlobs 75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 76 (newHeader, 77 newDecoder, 78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 79 self.memFlags, [], base) |
| 83 | 80 |
| 84 if add: 85 op = " +" 86 else: 87 op = " -" | 81 header_output += newHeader 82 decoder_output += newDecoder 83 exec_output += newExec |
| 88 | 84 |
| 89 offset = op + " imm" 90 eaCode = "EA = Base" 91 if not post: 92 eaCode += offset 93 eaCode += ";" | 85 class RfeInst(LoadInst): 86 decConstBase = 'Rfe' |
| 94 | 87 |
| 95 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] 96 if user: 97 memFlags.append("ArmISA::TLB::UserMode") | 88 def __init__(self, mnem, post, add, writeback): 89 super(RfeInst, self).__init__(mnem, post, add, writeback) 90 self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8) |
| 98 | 91 |
| 99 if prefetch: 100 Name = "%s_%s" % (mnem.upper(), Name) 101 memFlags.append("Request::PREFETCH") | 92 self.memFlags.append("ArmISA::TLB::AlignWord") 93 94 def emit(self): 95 offset = 0 96 if self.post != self.add: 97 offset += 4 98 if not self.add: 99 offset -= 8 100 self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset 101 102 wbDiff = -8 103 if self.add: 104 wbDiff = 8 |
| 102 accCode = ''' | 105 accCode = ''' |
| 103 uint64_t temp = Mem%s;\n 104 temp = temp; 105 ''' % buildMemSuffix(sign, size) 106 elif vldr: 107 Name = "%s_%s" % (mnem.upper(), Name) 108 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" % \ 109 buildMemSuffix(sign, size) 110 else: 111 if ldrex: 112 memFlags.append("Request::LLSC") 113 Name = "%s_%s" % (mnem.upper(), Name) 114 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \ 115 buildMemSuffix(sign, size) | 106 CPSR cpsr = Cpsr; 107 SCTLR sctlr = Sctlr; 108 NPC = cSwap<uint32_t>(Mem.ud, cpsr.e); 109 uint32_t newCpsr = 110 cpsrWriteByInstr(cpsr | CondCodes, 111 cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), 112 0xF, true, sctlr.nmfi); 113 Cpsr = ~CondCodesMask & newCpsr; 114 CondCodes = CondCodesMask & newCpsr; 115 ''' 116 if self.writeback: 117 accCode += "Base = Base + %s;\n" % wbDiff 118 self.codeBlobs["memacc_code"] = accCode |
| 116 | 119 |
| 117 if not prefetch and not ldrex and not vldr: 118 memFlags.append("ArmISA::TLB::AllowUnaligned") | 120 self.emitHelper('RfeOp') |
| 119 | 121 |
| 120 if writeback: 121 accCode += "Base = Base %s;\n" % offset 122 base = buildMemBase("MemoryImm", post, writeback) | 122 class LoadImmInst(LoadInst): 123 def __init__(self, *args, **kargs): 124 super(LoadImmInst, self).__init__(*args, **kargs) 125 self.offset = self.op + " imm" |
| 123 | 126 |
| 124 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) | 127 class LoadRegInst(LoadInst): 128 def __init__(self, *args, **kargs): 129 super(LoadRegInst, self).__init__(*args, **kargs) 130 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 131 " shiftType, CondCodes<29:>)" |
| 125 | 132 |
| 126 def buildRfeLoad(mnem, post, add, writeback): 127 name = mnem 128 Name = "RFE_" + loadImmClassName(post, add, writeback, 8) | 133 class LoadSingle(LoadInst): 134 def __init__(self, *args, **kargs): 135 super(LoadSingle, self).__init__(*args, **kargs) |
| 129 | 136 |
| 130 offset = 0 131 if post != add: 132 offset += 4 133 if not add: 134 offset -= 8 | 137 # Build the default class name 138 self.Name = self.nameFunc(self.post, self.add, self.writeback, 139 self.size, self.sign, self.user) |
| 135 | 140 |
| 136 eaCode = "EA = Base + %d;" % offset | 141 # Add memory request flags where necessary 142 self.memFlags.append("%d" % (self.size - 1)) 143 if self.user: 144 self.memFlags.append("ArmISA::TLB::UserMode") |
| 137 | 145 |
| 138 wbDiff = -8 139 if add: 140 wbDiff = 8 141 accCode = ''' 142 CPSR cpsr = Cpsr; 143 SCTLR sctlr = Sctlr; 144 NPC = cSwap<uint32_t>(Mem.ud, cpsr.e); 145 uint32_t newCpsr = 146 cpsrWriteByInstr(cpsr | CondCodes, 147 cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), 148 0xF, true, sctlr.nmfi); 149 Cpsr = ~CondCodesMask & newCpsr; 150 CondCodes = CondCodesMask & newCpsr; 151 ''' 152 if writeback: 153 accCode += "Base = Base + %s;\n" % wbDiff | 146 if self.flavor == "prefetch": 147 self.memFlags.append("Request::PREFETCH") 148 elif self.flavor == "exclusive": 149 self.memFlags.append("Request::LLSC") 150 elif self.flavor == "normal": 151 self.memFlags.append("ArmISA::TLB::AllowUnaligned") |
| 154 | 152 |
| 155 global header_output, decoder_output, exec_output | 153 # Disambiguate the class name for different flavors of loads 154 if self.flavor != "normal": 155 self.Name = "%s_%s" % (self.name.upper(), self.Name) |
| 156 | 156 |
| 157 (newHeader, 158 newDecoder, 159 newExec) = RfeBase(name, Name, eaCode, accCode, 160 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], []) | 157 def emit(self): 158 # Address compuation code 159 eaCode = "EA = Base" 160 if not self.post: 161 eaCode += self.offset 162 eaCode += ";" 163 self.codeBlobs["ea_code"] = eaCode |
| 161 | 164 |
| 162 header_output += newHeader 163 decoder_output += newDecoder 164 exec_output += newExec | 165 # Code that actually handles the access 166 if self.flavor == "prefetch": 167 accCode = 'uint64_t temp = Mem%s; temp = temp;' 168 elif self.flavor == "fp": 169 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" 170 else: 171 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" 172 accCode = accCode % buildMemSuffix(self.sign, self.size) |
| 165 | 173 |
| 166 def buildRegLoad(mnem, post, add, writeback, size=4, sign=False, \ 167 user=False, prefetch=False): 168 name = mnem 169 Name = loadRegClassName(post, add, writeback, 170 size, sign, user) | 174 if self.writeback: 175 accCode += "Base = Base %s;\n" % self.offset |
| 171 | 176 |
| 172 if add: 173 op = " +" 174 else: 175 op = " -" | 177 self.codeBlobs["memacc_code"] = accCode |
| 176 | 178 |
| 177 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 178 " shiftType, CondCodes<29:>)" 179 eaCode = "EA = Base" 180 if not post: 181 eaCode += offset 182 eaCode += ";" | 179 # Push it out to the output files 180 base = buildMemBase(self.basePrefix, self.post, self.writeback) 181 self.emitHelper(base) |
| 183 | 182 |
| 184 memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"] 185 if user: 186 memFlags.append("ArmISA::TLB::UserMode") | 183 def loadImmClassName(post, add, writeback, size=4, sign=False, user=False): 184 return memClassName("LOAD_IMM", post, add, writeback, size, sign, user) |
| 187 | 185 |
| 188 if prefetch: 189 Name = "%s_%s" % (mnem.upper(), Name) 190 memFlags.append("Request::PREFETCH") 191 accCode = ''' 192 uint64_t temp = Mem%s;\n 193 temp = temp; 194 ''' % buildMemSuffix(sign, size) 195 else: 196 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \ 197 buildMemSuffix(sign, size) 198 if writeback: 199 accCode += "Base = Base %s;\n" % offset | 186 class LoadImm(LoadImmInst, LoadSingle): 187 decConstBase = 'LoadStoreImm' 188 basePrefix = 'MemoryImm' 189 nameFunc = staticmethod(loadImmClassName) |
| 200 | 190 |
| 201 if not prefetch: 202 memFlags.append("ArmISA::TLB::AllowUnaligned") | 191 def loadRegClassName(post, add, writeback, size=4, sign=False, user=False): 192 return memClassName("LOAD_REG", post, add, writeback, size, sign, user) |
| 203 | 193 |
| 204 base = buildMemBase("MemoryReg", post, writeback) | 194 class LoadReg(LoadRegInst, LoadSingle): 195 decConstBase = 'LoadStoreReg' 196 basePrefix = 'MemoryReg' 197 nameFunc = staticmethod(loadRegClassName) |
| 205 | 198 |
| 206 emitLoad(name, Name, False, eaCode, accCode, \ 207 memFlags, [], base) | 199 class LoadDouble(LoadInst): 200 def __init__(self, *args, **kargs): 201 super(LoadDouble, self).__init__(*args, **kargs) |
| 208 | 202 |
| 209 def buildDoubleImmLoad(mnem, post, add, writeback, \ 210 ldrex=False, vldr=False): 211 name = mnem 212 Name = loadDoubleImmClassName(post, add, writeback) | 203 # Build the default class name 204 self.Name = self.nameFunc(self.post, self.add, self.writeback) |
| 213 | 205 |
| 214 if add: 215 op = " +" 216 else: 217 op = " -" | 206 # Add memory request flags where necessary 207 if self.flavor == "exclusive": 208 self.memFlags.append("Request::LLSC") 209 self.memFlags.append("ArmISA::TLB::AlignWord") |
| 218 | 210 |
| 219 offset = op + " imm" 220 eaCode = "EA = Base" 221 if not post: 222 eaCode += offset 223 eaCode += ";" | 211 # Disambiguate the class name for different flavors of loads 212 if self.flavor != "normal": 213 self.Name = "%s_%s" % (self.name.upper(), self.Name) |
| 224 | 214 |
| 225 if not vldr: 226 accCode = ''' 227 CPSR cpsr = Cpsr; 228 Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 229 Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 230 ''' 231 else: 232 accCode = ''' 233 uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); 234 FpDest.uw = (uint32_t)swappedMem; 235 FpDest2.uw = (uint32_t)(swappedMem >> 32); 236 ''' 237 if ldrex: 238 memFlags = ["Request::LLSC"] 239 else: 240 memFlags = [] 241 if ldrex or vldr: 242 Name = "%s_%s" % (mnem.upper(), Name) 243 if writeback: 244 accCode += "Base = Base %s;\n" % offset 245 base = buildMemBase("MemoryDImm", post, writeback) | 215 def emit(self): 216 # Address computation code 217 eaCode = "EA = Base" 218 if not self.post: 219 eaCode += self.offset 220 eaCode += ";" 221 self.codeBlobs["ea_code"] = eaCode |
| 246 | 222 |
| 247 memFlags.extend(["ArmISA::TLB::MustBeOne", 248 "ArmISA::TLB::AlignWord"]) | 223 # Code that actually handles the access 224 if self.flavor != "fp": 225 accCode = ''' 226 CPSR cpsr = Cpsr; 227 Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 228 Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 229 ''' 230 else: 231 accCode = ''' 232 uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); 233 FpDest.uw = (uint32_t)swappedMem; 234 FpDest2.uw = (uint32_t)(swappedMem >> 32); 235 ''' |
| 249 | 236 |
| 250 emitLoad(name, Name, True, eaCode, accCode, \ 251 memFlags, [], base, double=True) | 237 if self.writeback: 238 accCode += "Base = Base %s;\n" % self.offset |
| 252 | 239 |
| 253 def buildDoubleRegLoad(mnem, post, add, writeback): 254 name = mnem 255 Name = loadDoubleRegClassName(post, add, writeback) | 240 self.codeBlobs["memacc_code"] = accCode |
| 256 | 241 |
| 257 if add: 258 op = " +" 259 else: 260 op = " -" | 242 # Push it out to the output files 243 base = buildMemBase(self.basePrefix, self.post, self.writeback) 244 self.emitHelper(base) |
| 261 | 245 |
| 262 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 263 " shiftType, CondCodes<29:>)" 264 eaCode = "EA = Base" 265 if not post: 266 eaCode += offset 267 eaCode += ";" | 246 def loadDoubleImmClassName(post, add, writeback): 247 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) |
| 268 | 248 |
| 269 accCode = ''' 270 CPSR cpsr = Cpsr; 271 Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 272 Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 273 ''' 274 if writeback: 275 accCode += "Base = Base %s;\n" % offset 276 base = buildMemBase("MemoryDReg", post, writeback) | 249 class LoadDoubleImm(LoadImmInst, LoadDouble): 250 decConstBase = 'LoadStoreDImm' 251 basePrefix = 'MemoryDImm' 252 nameFunc = staticmethod(loadDoubleImmClassName) |
| 277 | 253 |
| 278 emitLoad(name, Name, False, eaCode, accCode, 279 ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"], 280 [], base, double=True) | 254 def loadDoubleRegClassName(post, add, writeback): 255 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) |
| 281 | 256 |
| 257 class LoadDoubleReg(LoadRegInst, LoadDouble): 258 decConstBase = 'LoadStoreDReg' 259 basePrefix = 'MemoryDReg' 260 nameFunc = staticmethod(loadDoubleRegClassName) 261 |
|
| 282 def buildLoads(mnem, size=4, sign=False, user=False): | 262 def buildLoads(mnem, size=4, sign=False, user=False): |
| 283 buildImmLoad(mnem, True, True, True, size, sign, user) 284 buildRegLoad(mnem, True, True, True, size, sign, user) 285 buildImmLoad(mnem, True, False, True, size, sign, user) 286 buildRegLoad(mnem, True, False, True, size, sign, user) 287 buildImmLoad(mnem, False, True, True, size, sign, user) 288 buildRegLoad(mnem, False, True, True, size, sign, user) 289 buildImmLoad(mnem, False, False, True, size, sign, user) 290 buildRegLoad(mnem, False, False, True, size, sign, user) 291 buildImmLoad(mnem, False, True, False, size, sign, user) 292 buildRegLoad(mnem, False, True, False, size, sign, user) 293 buildImmLoad(mnem, False, False, False, size, sign, user) 294 buildRegLoad(mnem, False, False, False, size, sign, user) | 263 LoadImm(mnem, True, True, True, size, sign, user).emit() 264 LoadReg(mnem, True, True, True, size, sign, user).emit() 265 LoadImm(mnem, True, False, True, size, sign, user).emit() 266 LoadReg(mnem, True, False, True, size, sign, user).emit() 267 LoadImm(mnem, False, True, True, size, sign, user).emit() 268 LoadReg(mnem, False, True, True, size, sign, user).emit() 269 LoadImm(mnem, False, False, True, size, sign, user).emit() 270 LoadReg(mnem, False, False, True, size, sign, user).emit() 271 LoadImm(mnem, False, True, False, size, sign, user).emit() 272 LoadReg(mnem, False, True, False, size, sign, user).emit() 273 LoadImm(mnem, False, False, False, size, sign, user).emit() 274 LoadReg(mnem, False, False, False, size, sign, user).emit() |
| 295 296 def buildDoubleLoads(mnem): | 275 276 def buildDoubleLoads(mnem): |
| 297 buildDoubleImmLoad(mnem, True, True, True) 298 buildDoubleRegLoad(mnem, True, True, True) 299 buildDoubleImmLoad(mnem, True, False, True) 300 buildDoubleRegLoad(mnem, True, False, True) 301 buildDoubleImmLoad(mnem, False, True, True) 302 buildDoubleRegLoad(mnem, False, True, True) 303 buildDoubleImmLoad(mnem, False, False, True) 304 buildDoubleRegLoad(mnem, False, False, True) 305 buildDoubleImmLoad(mnem, False, True, False) 306 buildDoubleRegLoad(mnem, False, True, False) 307 buildDoubleImmLoad(mnem, False, False, False) 308 buildDoubleRegLoad(mnem, False, False, False) | 277 LoadDoubleImm(mnem, True, True, True).emit() 278 LoadDoubleReg(mnem, True, True, True).emit() 279 LoadDoubleImm(mnem, True, False, True).emit() 280 LoadDoubleReg(mnem, True, False, True).emit() 281 LoadDoubleImm(mnem, False, True, True).emit() 282 LoadDoubleReg(mnem, False, True, True).emit() 283 LoadDoubleImm(mnem, False, False, True).emit() 284 LoadDoubleReg(mnem, False, False, True).emit() 285 LoadDoubleImm(mnem, False, True, False).emit() 286 LoadDoubleReg(mnem, False, True, False).emit() 287 LoadDoubleImm(mnem, False, False, False).emit() 288 LoadDoubleReg(mnem, False, False, False).emit() |
| 309 310 def buildRfeLoads(mnem): | 289 290 def buildRfeLoads(mnem): |
| 311 buildRfeLoad(mnem, True, True, True) 312 buildRfeLoad(mnem, True, True, False) 313 buildRfeLoad(mnem, True, False, True) 314 buildRfeLoad(mnem, True, False, False) 315 buildRfeLoad(mnem, False, True, True) 316 buildRfeLoad(mnem, False, True, False) 317 buildRfeLoad(mnem, False, False, True) 318 buildRfeLoad(mnem, False, False, False) | 291 RfeInst(mnem, True, True, True).emit() 292 RfeInst(mnem, True, True, False).emit() 293 RfeInst(mnem, True, False, True).emit() 294 RfeInst(mnem, True, False, False).emit() 295 RfeInst(mnem, False, True, True).emit() 296 RfeInst(mnem, False, True, False).emit() 297 RfeInst(mnem, False, False, True).emit() 298 RfeInst(mnem, False, False, False).emit() |
| 319 320 def buildPrefetches(mnem): | 299 300 def buildPrefetches(mnem): |
| 321 buildRegLoad(mnem, False, False, False, size=1, prefetch=True) 322 buildImmLoad(mnem, False, False, False, size=1, prefetch=True) 323 buildRegLoad(mnem, False, True, False, size=1, prefetch=True) 324 buildImmLoad(mnem, False, True, False, size=1, prefetch=True) | 301 LoadReg(mnem, False, False, False, size=1, flavor="prefetch").emit() 302 LoadImm(mnem, False, False, False, size=1, flavor="prefetch").emit() 303 LoadReg(mnem, False, True, False, size=1, flavor="prefetch").emit() 304 LoadImm(mnem, False, True, False, size=1, flavor="prefetch").emit() |
| 325 326 buildLoads("ldr") 327 buildLoads("ldrt", user=True) 328 buildLoads("ldrb", size=1) 329 buildLoads("ldrbt", size=1, user=True) 330 buildLoads("ldrsb", size=1, sign=True) 331 buildLoads("ldrsbt", size=1, sign=True, user=True) 332 buildLoads("ldrh", size=2) --- 4 unchanged lines hidden (view full) --- 337 buildDoubleLoads("ldrd") 338 339 buildRfeLoads("rfe") 340 341 buildPrefetches("pld") 342 buildPrefetches("pldw") 343 buildPrefetches("pli") 344 | 305 306 buildLoads("ldr") 307 buildLoads("ldrt", user=True) 308 buildLoads("ldrb", size=1) 309 buildLoads("ldrbt", size=1, user=True) 310 buildLoads("ldrsb", size=1, sign=True) 311 buildLoads("ldrsbt", size=1, sign=True, user=True) 312 buildLoads("ldrh", size=2) --- 4 unchanged lines hidden (view full) --- 317 buildDoubleLoads("ldrd") 318 319 buildRfeLoads("rfe") 320 321 buildPrefetches("pld") 322 buildPrefetches("pldw") 323 buildPrefetches("pli") 324 |
| 345 buildImmLoad("ldrex", False, True, False, size=4, ldrex=True) 346 buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True) 347 buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True) 348 buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True) | 325 LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit() 326 LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit() 327 LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit() 328 LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit() |
| 349 | 329 |
| 350 buildImmLoad("vldr", False, True, False, size=4, vldr=True) 351 buildImmLoad("vldr", False, False, False, size=4, vldr=True) 352 buildDoubleImmLoad("vldr", False, True, False, vldr=True) 353 buildDoubleImmLoad("vldr", False, False, False, vldr=True) | 330 LoadImm("vldr", False, True, False, size=4, flavor="fp").emit() 331 LoadImm("vldr", False, False, False, size=4, flavor="fp").emit() 332 LoadDoubleImm("vldr", False, True, False, flavor="fp").emit() 333 LoadDoubleImm("vldr", False, False, False, flavor="fp").emit() |
| 354}}; | 334}}; |