ldr.isa (7294:fda2c00880db) ldr.isa (7296:27c60324ec4d)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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99 accCode = '''
100 uint64_t temp = Mem%s;\n
101 temp = temp;
102 ''' % buildMemSuffix(sign, size)
103 else:
104 if ldrex:
105 memFlags.append("Request::LLSC")
106 Name = "%s_%s" % (mnem.upper(), Name)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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99 accCode = '''
100 uint64_t temp = Mem%s;\n
101 temp = temp;
102 ''' % buildMemSuffix(sign, size)
103 else:
104 if ldrex:
105 memFlags.append("Request::LLSC")
106 Name = "%s_%s" % (mnem.upper(), Name)
107 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
107 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \
108 buildMemSuffix(sign, size)
108
109 if not prefetch and not ldrex:
110 memFlags.append("ArmISA::TLB::AllowUnaligned")
111
112 if writeback:
113 accCode += "Base = Base %s;\n" % offset
114 base = buildMemBase("MemoryImm", post, writeback)
115

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126 offset -= 8
127
128 eaCode = "EA = Base + %d;" % offset
129
130 wbDiff = -8
131 if add:
132 wbDiff = 8
133 accCode = '''
109
110 if not prefetch and not ldrex:
111 memFlags.append("ArmISA::TLB::AllowUnaligned")
112
113 if writeback:
114 accCode += "Base = Base %s;\n" % offset
115 base = buildMemBase("MemoryImm", post, writeback)
116

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127 offset -= 8
128
129 eaCode = "EA = Base + %d;" % offset
130
131 wbDiff = -8
132 if add:
133 wbDiff = 8
134 accCode = '''
134 NPC = bits(Mem.ud, 31, 0);
135 uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes,
136 bits(Mem.ud, 63, 32),
137 0xF, true);
135 CPSR cpsr = Cpsr;
136 NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
137 uint32_t newCpsr =
138 cpsrWriteByInstr(cpsr | CondCodes,
139 cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
140 0xF, true);
138 Cpsr = ~CondCodesMask & newCpsr;
139 CondCodes = CondCodesMask & newCpsr;
140 '''
141 if writeback:
142 accCode += "Base = Base + %s;\n" % wbDiff
143
144 global header_output, decoder_output, exec_output
145

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174 if prefetch:
175 Name = "%s_%s" % (mnem.upper(), Name)
176 memFlags.append("Request::PREFETCH")
177 accCode = '''
178 uint64_t temp = Mem%s;\n
179 temp = temp;
180 ''' % buildMemSuffix(sign, size)
181 else:
141 Cpsr = ~CondCodesMask & newCpsr;
142 CondCodes = CondCodesMask & newCpsr;
143 '''
144 if writeback:
145 accCode += "Base = Base + %s;\n" % wbDiff
146
147 global header_output, decoder_output, exec_output
148

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177 if prefetch:
178 Name = "%s_%s" % (mnem.upper(), Name)
179 memFlags.append("Request::PREFETCH")
180 accCode = '''
181 uint64_t temp = Mem%s;\n
182 temp = temp;
183 ''' % buildMemSuffix(sign, size)
184 else:
182 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
185 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \
186 buildMemSuffix(sign, size)
183 if writeback:
184 accCode += "Base = Base %s;\n" % offset
185
186 if not prefetch:
187 memFlags.append("ArmISA::TLB::AllowUnaligned")
188
189 base = buildMemBase("MemoryReg", post, writeback)
190

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202
203 offset = op + " imm"
204 eaCode = "EA = Base"
205 if not post:
206 eaCode += offset
207 eaCode += ";"
208
209 accCode = '''
187 if writeback:
188 accCode += "Base = Base %s;\n" % offset
189
190 if not prefetch:
191 memFlags.append("ArmISA::TLB::AllowUnaligned")
192
193 base = buildMemBase("MemoryReg", post, writeback)
194

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206
207 offset = op + " imm"
208 eaCode = "EA = Base"
209 if not post:
210 eaCode += offset
211 eaCode += ";"
212
213 accCode = '''
210 Dest = bits(Mem.ud, 31, 0);
211 Dest2 = bits(Mem.ud, 63, 32);
214 CPSR cpsr = Cpsr;
215 Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
216 Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
212 '''
213 if ldrex:
214 memFlags = ["Request::LLSC"]
215 Name = "%s_%s" % (mnem.upper(), Name)
216 else:
217 memFlags = []
218 if writeback:
219 accCode += "Base = Base %s;\n" % offset

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237 offset = op + " shift_rm_imm(Index, shiftAmt," + \
238 " shiftType, CondCodes<29:>)"
239 eaCode = "EA = Base"
240 if not post:
241 eaCode += offset
242 eaCode += ";"
243
244 accCode = '''
217 '''
218 if ldrex:
219 memFlags = ["Request::LLSC"]
220 Name = "%s_%s" % (mnem.upper(), Name)
221 else:
222 memFlags = []
223 if writeback:
224 accCode += "Base = Base %s;\n" % offset

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242 offset = op + " shift_rm_imm(Index, shiftAmt," + \
243 " shiftType, CondCodes<29:>)"
244 eaCode = "EA = Base"
245 if not post:
246 eaCode += offset
247 eaCode += ";"
248
249 accCode = '''
245 Dest = bits(Mem.ud, 31, 0);
246 Dest2 = bits(Mem.ud, 63, 32);
250 CPSR cpsr = Cpsr;
251 Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
252 Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
247 '''
248 if writeback:
249 accCode += "Base = Base %s;\n" % offset
250 base = buildMemBase("MemoryDReg", post, writeback)
251
252 emitLoad(name, Name, False, eaCode, accCode,
253 ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"],
254 [], base, double=True)

--- 69 unchanged lines hidden --- 		253 '''
254 if writeback:
255 accCode += "Base = Base %s;\n" % offset
256 base = buildMemBase("MemoryDReg", post, writeback)
257
258 emitLoad(name, Name, False, eaCode, accCode,
259 ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"],
260 [], base, double=True)

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