ldr.isa (7279:157b02cc0ba1) ldr.isa (7292:f4d99c45743e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 98 unchanged lines hidden (view full) ---

107 memFlags = []
108 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
109 if writeback:
110 accCode += "Base = Base %s;\n" % offset
111 base = buildMemBase("MemoryImm", post, writeback)
112
113 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
114
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 98 unchanged lines hidden (view full) ---

107 memFlags = []
108 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
109 if writeback:
110 accCode += "Base = Base %s;\n" % offset
111 base = buildMemBase("MemoryImm", post, writeback)
112
113 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
114
115 def buildRfeLoad(mnem, post, add, writeback):
116 name = mnem
117 Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
118
119 offset = 0
120 if post != add:
121 offset += 4
122 if not add:
123 offset -= 8
124
125 eaCode = "EA = Base + %d;" % offset
126
127 wbDiff = -8
128 if add:
129 wbDiff = 8
130 accCode = '''
131 NPC = bits(Mem.ud, 31, 0);
132 uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes,
133 bits(Mem.ud, 63, 32),
134 0xF, true);
135 Cpsr = ~CondCodesMask & newCpsr;
136 CondCodes = CondCodesMask & newCpsr;
137 '''
138 if writeback:
139 accCode += "Base = Base + %s;\n" % wbDiff
140
141 global header_output, decoder_output, exec_output
142
143 (newHeader,
144 newDecoder,
145 newExec) = RfeBase(name, Name, eaCode, accCode, [], [])
146
147 header_output += newHeader
148 decoder_output += newDecoder
149 exec_output += newExec
150
115 def buildRegLoad(mnem, post, add, writeback, \
116 size=4, sign=False, user=False, prefetch=False):
117 name = mnem
118 Name = loadRegClassName(post, add, writeback,
119 size, sign, user)
120
121 if add:
122 op = " +"

--- 105 unchanged lines hidden (view full) ---

228 buildDoubleRegLoad(mnem, False, True, True)
229 buildDoubleImmLoad(mnem, False, False, True)
230 buildDoubleRegLoad(mnem, False, False, True)
231 buildDoubleImmLoad(mnem, False, True, False)
232 buildDoubleRegLoad(mnem, False, True, False)
233 buildDoubleImmLoad(mnem, False, False, False)
234 buildDoubleRegLoad(mnem, False, False, False)
235
151 def buildRegLoad(mnem, post, add, writeback, \
152 size=4, sign=False, user=False, prefetch=False):
153 name = mnem
154 Name = loadRegClassName(post, add, writeback,
155 size, sign, user)
156
157 if add:
158 op = " +"

--- 105 unchanged lines hidden (view full) ---

264 buildDoubleRegLoad(mnem, False, True, True)
265 buildDoubleImmLoad(mnem, False, False, True)
266 buildDoubleRegLoad(mnem, False, False, True)
267 buildDoubleImmLoad(mnem, False, True, False)
268 buildDoubleRegLoad(mnem, False, True, False)
269 buildDoubleImmLoad(mnem, False, False, False)
270 buildDoubleRegLoad(mnem, False, False, False)
271
272 def buildRfeLoads(mnem):
273 buildRfeLoad(mnem, True, True, True)
274 buildRfeLoad(mnem, True, True, False)
275 buildRfeLoad(mnem, True, False, True)
276 buildRfeLoad(mnem, True, False, False)
277 buildRfeLoad(mnem, False, True, True)
278 buildRfeLoad(mnem, False, True, False)
279 buildRfeLoad(mnem, False, False, True)
280 buildRfeLoad(mnem, False, False, False)
281
236 def buildPrefetches(mnem):
237 buildRegLoad(mnem, False, False, False, size=1, prefetch=True)
238 buildImmLoad(mnem, False, False, False, size=1, prefetch=True)
239 buildRegLoad(mnem, False, True, False, size=1, prefetch=True)
240 buildImmLoad(mnem, False, True, False, size=1, prefetch=True)
241
242 buildLoads("ldr")
243 buildLoads("ldrt", user=True)
244 buildLoads("ldrb", size=1)
245 buildLoads("ldrbt", size=1, user=True)
246 buildLoads("ldrsb", size=1, sign=True)
247 buildLoads("ldrsbt", size=1, sign=True, user=True)
248 buildLoads("ldrh", size=2)
249 buildLoads("ldrht", size=2, user=True)
250 buildLoads("hdrsh", size=2, sign=True)
251 buildLoads("ldrsht", size=2, sign=True, user=True)
252
253 buildDoubleLoads("ldrd")
254
282 def buildPrefetches(mnem):
283 buildRegLoad(mnem, False, False, False, size=1, prefetch=True)
284 buildImmLoad(mnem, False, False, False, size=1, prefetch=True)
285 buildRegLoad(mnem, False, True, False, size=1, prefetch=True)
286 buildImmLoad(mnem, False, True, False, size=1, prefetch=True)
287
288 buildLoads("ldr")
289 buildLoads("ldrt", user=True)
290 buildLoads("ldrb", size=1)
291 buildLoads("ldrbt", size=1, user=True)
292 buildLoads("ldrsb", size=1, sign=True)
293 buildLoads("ldrsbt", size=1, sign=True, user=True)
294 buildLoads("ldrh", size=2)
295 buildLoads("ldrht", size=2, user=True)
296 buildLoads("hdrsh", size=2, sign=True)
297 buildLoads("ldrsht", size=2, sign=True, user=True)
298
299 buildDoubleLoads("ldrd")
300
301 buildRfeLoads("rfe")
302
255 buildPrefetches("pld")
256 buildPrefetches("pldw")
257 buildPrefetches("pli")
258
259 buildImmLoad("ldrex", False, True, False, size=4, ldrex=True)
260 buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True)
261 buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True)
262 buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True)
263}};
303 buildPrefetches("pld")
304 buildPrefetches("pldw")
305 buildPrefetches("pli")
306
307 buildImmLoad("ldrex", False, True, False, size=4, ldrex=True)
308 buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True)
309 buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True)
310 buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True)
311}};