ldr.isa (7244:d7fa6d111644) ldr.isa (7279:157b02cc0ba1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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54 size, sign, user)
55
56 def loadDoubleImmClassName(post, add, writeback):
57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
58
59 def loadDoubleRegClassName(post, add, writeback):
60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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54 size, sign, user)
55
56 def loadDoubleImmClassName(post, add, writeback):
57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
58
59 def loadDoubleRegClassName(post, add, writeback):
60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
62 def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
62 def emitLoad(name, Name, imm, eaCode, accCode, \
63 memFlags, instFlags, base, double=False):
63 global header_output, decoder_output, exec_output
64
65 (newHeader,
66 newDecoder,
67 newExec) = loadStoreBase(name, Name, imm,
68 eaCode, accCode,
64 global header_output, decoder_output, exec_output
65
66 (newHeader,
67 newDecoder,
68 newExec) = loadStoreBase(name, Name, imm,
69 eaCode, accCode,
69 memFlags, instFlags,
70 memFlags, instFlags, double,
70 base, execTemplateBase = 'Load')
71
72 header_output += newHeader
73 decoder_output += newDecoder
74 exec_output += newExec
75
76 def buildImmLoad(mnem, post, add, writeback, \
77 size=4, sign=False, user=False, \

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138 ''' % buildMemSuffix(sign, size)
139 else:
140 memFlags = []
141 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
142 if writeback:
143 accCode += "Base = Base %s;\n" % offset
144 base = buildMemBase("MemoryReg", post, writeback)
145
71 base, execTemplateBase = 'Load')
72
73 header_output += newHeader
74 decoder_output += newDecoder
75 exec_output += newExec
76
77 def buildImmLoad(mnem, post, add, writeback, \
78 size=4, sign=False, user=False, \

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139 ''' % buildMemSuffix(sign, size)
140 else:
141 memFlags = []
142 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
143 if writeback:
144 accCode += "Base = Base %s;\n" % offset
145 base = buildMemBase("MemoryReg", post, writeback)
146
146 emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base)
147 emitLoad(name, Name, False, eaCode, accCode, \
148 memFlags, [], base)
147
148 def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False):
149 name = mnem
150 Name = loadDoubleImmClassName(post, add, writeback)
151
152 if add:
153 op = " +"
154 else:
155 op = " -"
156
157 offset = op + " imm"
158 eaCode = "EA = Base"
159 if not post:
160 eaCode += offset
161 eaCode += ";"
162
163 accCode = '''
149
150 def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False):
151 name = mnem
152 Name = loadDoubleImmClassName(post, add, writeback)
153
154 if add:
155 op = " +"
156 else:
157 op = " -"
158
159 offset = op + " imm"
160 eaCode = "EA = Base"
161 if not post:
162 eaCode += offset
163 eaCode += ";"
164
165 accCode = '''
164 Rdo = bits(Mem.ud, 31, 0);
165 Rde = bits(Mem.ud, 63, 32);
166 Dest = bits(Mem.ud, 31, 0);
167 Dest2 = bits(Mem.ud, 63, 32);
166 '''
167 if ldrex:
168 memFlags = ["Request::LLSC"]
169 Name = "%s_%s" % (mnem.upper(), Name)
170 else:
171 memFlags = []
172 if writeback:
173 accCode += "Base = Base %s;\n" % offset
168 '''
169 if ldrex:
170 memFlags = ["Request::LLSC"]
171 Name = "%s_%s" % (mnem.upper(), Name)
172 else:
173 memFlags = []
174 if writeback:
175 accCode += "Base = Base %s;\n" % offset
174 base = buildMemBase("MemoryImm", post, writeback)
176 base = buildMemBase("MemoryDImm", post, writeback)
175
177
176 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
178 emitLoad(name, Name, True, eaCode, accCode, \
179 memFlags, [], base, double=True)
177
178 def buildDoubleRegLoad(mnem, post, add, writeback):
179 name = mnem
180 Name = loadDoubleRegClassName(post, add, writeback)
181
182 if add:
183 op = " +"
184 else:
185 op = " -"
186
187 offset = op + " shift_rm_imm(Index, shiftAmt," + \
188 " shiftType, CondCodes<29:>)"
189 eaCode = "EA = Base"
190 if not post:
191 eaCode += offset
192 eaCode += ";"
193
194 accCode = '''
180
181 def buildDoubleRegLoad(mnem, post, add, writeback):
182 name = mnem
183 Name = loadDoubleRegClassName(post, add, writeback)
184
185 if add:
186 op = " +"
187 else:
188 op = " -"
189
190 offset = op + " shift_rm_imm(Index, shiftAmt," + \
191 " shiftType, CondCodes<29:>)"
192 eaCode = "EA = Base"
193 if not post:
194 eaCode += offset
195 eaCode += ";"
196
197 accCode = '''
195 Rdo = bits(Mem.ud, 31, 0);
196 Rde = bits(Mem.ud, 63, 32);
198 Dest = bits(Mem.ud, 31, 0);
199 Dest2 = bits(Mem.ud, 63, 32);
197 '''
198 if writeback:
199 accCode += "Base = Base %s;\n" % offset
200 '''
201 if writeback:
202 accCode += "Base = Base %s;\n" % offset
200 base = buildMemBase("MemoryReg", post, writeback)
203 base = buildMemBase("MemoryDReg", post, writeback)
201
204
202 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
205 emitLoad(name, Name, False, eaCode, accCode,
206 [], [], base, double=True)
203
204 def buildLoads(mnem, size=4, sign=False, user=False):
205 buildImmLoad(mnem, True, True, True, size, sign, user)
206 buildRegLoad(mnem, True, True, True, size, sign, user)
207 buildImmLoad(mnem, True, False, True, size, sign, user)
208 buildRegLoad(mnem, True, False, True, size, sign, user)
209 buildImmLoad(mnem, False, True, True, size, sign, user)
210 buildRegLoad(mnem, False, True, True, size, sign, user)

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208 def buildLoads(mnem, size=4, sign=False, user=False):
209 buildImmLoad(mnem, True, True, True, size, sign, user)
210 buildRegLoad(mnem, True, True, True, size, sign, user)
211 buildImmLoad(mnem, True, False, True, size, sign, user)
212 buildRegLoad(mnem, True, False, True, size, sign, user)
213 buildImmLoad(mnem, False, True, True, size, sign, user)
214 buildRegLoad(mnem, False, True, True, size, sign, user)

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