ldr.isa (7128:01b4fff80dda) ldr.isa (7132:83b433d6e600)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 50 unchanged lines hidden (view full) ---

59 def loadDoubleRegClassName(post, add, writeback):
60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
62 def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
63 global header_output, decoder_output, exec_output
64
65 (newHeader,
66 newDecoder,
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 50 unchanged lines hidden (view full) ---

59 def loadDoubleRegClassName(post, add, writeback):
60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
62 def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
63 global header_output, decoder_output, exec_output
64
65 (newHeader,
66 newDecoder,
67 newExec) = newLoadStoreBase(name, Name, imm,
68 eaCode, accCode,
69 memFlags, instFlags,
70 base, execTemplateBase = 'Load')
67 newExec) = loadStoreBase(name, Name, imm,
68 eaCode, accCode,
69 memFlags, instFlags,
70 base, execTemplateBase = 'Load')
71
72 header_output += newHeader
73 decoder_output += newDecoder
74 exec_output += newExec
75
76 def buildImmLoad(mnem, post, add, writeback, \
77 size=4, sign=False, user=False):
78 name = mnem

--- 9 unchanged lines hidden (view full) ---

88 eaCode = "EA = Base"
89 if not post:
90 eaCode += offset
91 eaCode += ";"
92
93 accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
94 if writeback:
95 accCode += "Base = Base %s;\n" % offset
71
72 header_output += newHeader
73 decoder_output += newDecoder
74 exec_output += newExec
75
76 def buildImmLoad(mnem, post, add, writeback, \
77 size=4, sign=False, user=False):
78 name = mnem

--- 9 unchanged lines hidden (view full) ---

88 eaCode = "EA = Base"
89 if not post:
90 eaCode += offset
91 eaCode += ";"
92
93 accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
94 if writeback:
95 accCode += "Base = Base %s;\n" % offset
96 base = buildMemBase("MemoryNewImm", post, writeback)
96 base = buildMemBase("MemoryImm", post, writeback)
97
98 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
99
100 def buildRegLoad(mnem, post, add, writeback, \
101 size=4, sign=False, user=False):
102 name = mnem
103 Name = loadRegClassName(post, add, writeback,
104 size, sign, user)

--- 8 unchanged lines hidden (view full) ---

113 eaCode = "EA = Base"
114 if not post:
115 eaCode += offset
116 eaCode += ";"
117
118 accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
119 if writeback:
120 accCode += "Base = Base %s;\n" % offset
97
98 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
99
100 def buildRegLoad(mnem, post, add, writeback, \
101 size=4, sign=False, user=False):
102 name = mnem
103 Name = loadRegClassName(post, add, writeback,
104 size, sign, user)

--- 8 unchanged lines hidden (view full) ---

113 eaCode = "EA = Base"
114 if not post:
115 eaCode += offset
116 eaCode += ";"
117
118 accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
119 if writeback:
120 accCode += "Base = Base %s;\n" % offset
121 base = buildMemBase("MemoryNewReg", post, writeback)
121 base = buildMemBase("MemoryReg", post, writeback)
122
123 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
124
125 def buildDoubleImmLoad(mnem, post, add, writeback):
126 name = mnem
127 Name = loadDoubleImmClassName(post, add, writeback)
128
129 if add:

--- 8 unchanged lines hidden (view full) ---

138 eaCode += ";"
139
140 accCode = '''
141 Rdo = bits(Mem.ud, 31, 0);
142 Rde = bits(Mem.ud, 63, 32);
143 '''
144 if writeback:
145 accCode += "Base = Base %s;\n" % offset
122
123 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
124
125 def buildDoubleImmLoad(mnem, post, add, writeback):
126 name = mnem
127 Name = loadDoubleImmClassName(post, add, writeback)
128
129 if add:

--- 8 unchanged lines hidden (view full) ---

138 eaCode += ";"
139
140 accCode = '''
141 Rdo = bits(Mem.ud, 31, 0);
142 Rde = bits(Mem.ud, 63, 32);
143 '''
144 if writeback:
145 accCode += "Base = Base %s;\n" % offset
146 base = buildMemBase("MemoryNewImm", post, writeback)
146 base = buildMemBase("MemoryImm", post, writeback)
147
148 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
149
150 def buildDoubleRegLoad(mnem, post, add, writeback):
151 name = mnem
152 Name = loadDoubleRegClassName(post, add, writeback)
153
154 if add:

--- 9 unchanged lines hidden (view full) ---

164 eaCode += ";"
165
166 accCode = '''
167 Rdo = bits(Mem.ud, 31, 0);
168 Rde = bits(Mem.ud, 63, 32);
169 '''
170 if writeback:
171 accCode += "Base = Base %s;\n" % offset
147
148 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
149
150 def buildDoubleRegLoad(mnem, post, add, writeback):
151 name = mnem
152 Name = loadDoubleRegClassName(post, add, writeback)
153
154 if add:

--- 9 unchanged lines hidden (view full) ---

164 eaCode += ";"
165
166 accCode = '''
167 Rdo = bits(Mem.ud, 31, 0);
168 Rde = bits(Mem.ud, 63, 32);
169 '''
170 if writeback:
171 accCode += "Base = Base %s;\n" % offset
172 base = buildMemBase("MemoryNewReg", post, writeback)
172 base = buildMemBase("MemoryReg", post, writeback)
173
174 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
175
176 def buildLoads(mnem, size=4, sign=False, user=False):
177 buildImmLoad(mnem, True, True, True, size, sign, user)
178 buildRegLoad(mnem, True, True, True, size, sign, user)
179 buildImmLoad(mnem, True, False, True, size, sign, user)
180 buildRegLoad(mnem, True, False, True, size, sign, user)

--- 36 unchanged lines hidden --- 		173
174 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
175
176 def buildLoads(mnem, size=4, sign=False, user=False):
177 buildImmLoad(mnem, True, True, True, size, sign, user)
178 buildRegLoad(mnem, True, True, True, size, sign, user)
179 buildImmLoad(mnem, True, False, True, size, sign, user)
180 buildRegLoad(mnem, True, False, True, size, sign, user)

--- 36 unchanged lines hidden ---