ldr.isa (7119:5ad962dec52f) ldr.isa (7128:01b4fff80dda)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 39 unchanged lines hidden (view full) ---

48 return memClassName("LOAD_IMM", post, add, writeback,
49 size, sign, user)
50
51 def loadRegClassName(post, add, writeback, \
52 size=4, sign=False, user=False):
53 return memClassName("LOAD_REG", post, add, writeback,
54 size, sign, user)
55
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 39 unchanged lines hidden (view full) ---

48 return memClassName("LOAD_IMM", post, add, writeback,
49 size, sign, user)
50
51 def loadRegClassName(post, add, writeback, \
52 size=4, sign=False, user=False):
53 return memClassName("LOAD_REG", post, add, writeback,
54 size, sign, user)
55
56 def loadDoubleImmClassName(post, add, writeback):
57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
58
59 def loadDoubleRegClassName(post, add, writeback):
60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
56 def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
57 global header_output, decoder_output, exec_output
58
59 (newHeader,
60 newDecoder,
61 newExec) = newLoadStoreBase(name, Name, imm,
62 eaCode, accCode,
63 memFlags, instFlags,

--- 47 unchanged lines hidden (view full) ---

111
112 accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
113 if writeback:
114 accCode += "Base = Base %s;\n" % offset
115 base = buildMemBase("MemoryNewReg", post, writeback)
116
117 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
118
62 def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
63 global header_output, decoder_output, exec_output
64
65 (newHeader,
66 newDecoder,
67 newExec) = newLoadStoreBase(name, Name, imm,
68 eaCode, accCode,
69 memFlags, instFlags,

--- 47 unchanged lines hidden (view full) ---

117
118 accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
119 if writeback:
120 accCode += "Base = Base %s;\n" % offset
121 base = buildMemBase("MemoryNewReg", post, writeback)
122
123 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
124
125 def buildDoubleImmLoad(mnem, post, add, writeback):
126 name = mnem
127 Name = loadDoubleImmClassName(post, add, writeback)
128
129 if add:
130 op = " +"
131 else:
132 op = " -"
133
134 offset = op + " imm"
135 eaCode = "EA = Base"
136 if not post:
137 eaCode += offset
138 eaCode += ";"
139
140 accCode = '''
141 Rdo = bits(Mem.ud, 31, 0);
142 Rde = bits(Mem.ud, 63, 32);
143 '''
144 if writeback:
145 accCode += "Base = Base %s;\n" % offset
146 base = buildMemBase("MemoryNewImm", post, writeback)
147
148 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
149
150 def buildDoubleRegLoad(mnem, post, add, writeback):
151 name = mnem
152 Name = loadDoubleRegClassName(post, add, writeback)
153
154 if add:
155 op = " +"
156 else:
157 op = " -"
158
159 offset = op + " shift_rm_imm(Index, shiftAmt," + \
160 " shiftType, CondCodes<29:>)"
161 eaCode = "EA = Base"
162 if not post:
163 eaCode += offset
164 eaCode += ";"
165
166 accCode = '''
167 Rdo = bits(Mem.ud, 31, 0);
168 Rde = bits(Mem.ud, 63, 32);
169 '''
170 if writeback:
171 accCode += "Base = Base %s;\n" % offset
172 base = buildMemBase("MemoryNewReg", post, writeback)
173
174 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
175
119 def buildLoads(mnem, size=4, sign=False, user=False):
120 buildImmLoad(mnem, True, True, True, size, sign, user)
121 buildRegLoad(mnem, True, True, True, size, sign, user)
122 buildImmLoad(mnem, True, False, True, size, sign, user)
123 buildRegLoad(mnem, True, False, True, size, sign, user)
124 buildImmLoad(mnem, False, True, True, size, sign, user)
125 buildRegLoad(mnem, False, True, True, size, sign, user)
126 buildImmLoad(mnem, False, False, True, size, sign, user)
127 buildRegLoad(mnem, False, False, True, size, sign, user)
128 buildImmLoad(mnem, False, True, False, size, sign, user)
129 buildRegLoad(mnem, False, True, False, size, sign, user)
130 buildImmLoad(mnem, False, False, False, size, sign, user)
131 buildRegLoad(mnem, False, False, False, size, sign, user)
132
176 def buildLoads(mnem, size=4, sign=False, user=False):
177 buildImmLoad(mnem, True, True, True, size, sign, user)
178 buildRegLoad(mnem, True, True, True, size, sign, user)
179 buildImmLoad(mnem, True, False, True, size, sign, user)
180 buildRegLoad(mnem, True, False, True, size, sign, user)
181 buildImmLoad(mnem, False, True, True, size, sign, user)
182 buildRegLoad(mnem, False, True, True, size, sign, user)
183 buildImmLoad(mnem, False, False, True, size, sign, user)
184 buildRegLoad(mnem, False, False, True, size, sign, user)
185 buildImmLoad(mnem, False, True, False, size, sign, user)
186 buildRegLoad(mnem, False, True, False, size, sign, user)
187 buildImmLoad(mnem, False, False, False, size, sign, user)
188 buildRegLoad(mnem, False, False, False, size, sign, user)
189
190 def buildDoubleLoads(mnem):
191 buildDoubleImmLoad(mnem, True, True, True)
192 buildDoubleRegLoad(mnem, True, True, True)
193 buildDoubleImmLoad(mnem, True, False, True)
194 buildDoubleRegLoad(mnem, True, False, True)
195 buildDoubleImmLoad(mnem, False, True, True)
196 buildDoubleRegLoad(mnem, False, True, True)
197 buildDoubleImmLoad(mnem, False, False, True)
198 buildDoubleRegLoad(mnem, False, False, True)
199 buildDoubleImmLoad(mnem, False, True, False)
200 buildDoubleRegLoad(mnem, False, True, False)
201 buildDoubleImmLoad(mnem, False, False, False)
202 buildDoubleRegLoad(mnem, False, False, False)
203
133 buildLoads("ldr")
134 buildLoads("ldrt", user=True)
135 buildLoads("ldrb", size=1)
136 buildLoads("ldrbt", size=1, user=True)
137 buildLoads("ldrsb", size=1, sign=True)
138 buildLoads("ldrsbt", size=1, sign=True, user=True)
139 buildLoads("ldrh", size=2)
140 buildLoads("ldrht", size=2, user=True)
141 buildLoads("hdrsh", size=2, sign=True)
142 buildLoads("ldrsht", size=2, sign=True, user=True)
204 buildLoads("ldr")
205 buildLoads("ldrt", user=True)
206 buildLoads("ldrb", size=1)
207 buildLoads("ldrbt", size=1, user=True)
208 buildLoads("ldrsb", size=1, sign=True)
209 buildLoads("ldrsbt", size=1, sign=True, user=True)
210 buildLoads("ldrh", size=2)
211 buildLoads("ldrht", size=2, user=True)
212 buildLoads("hdrsh", size=2, sign=True)
213 buildLoads("ldrsht", size=2, sign=True, user=True)
214
215 buildDoubleLoads("ldrd")
143}};
216}};