1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 53 unchanged lines hidden (view full) --- 62 if self.add: 63 self.op = " +" 64 else: 65 self.op = " -" 66 67 self.memFlags = ["ArmISA::TLB::MustBeOne"] 68 self.codeBlobs = {"postacc_code" : ""} 69 |
70 def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None): |
71 72 global header_output, decoder_output, exec_output 73 74 codeBlobs = self.codeBlobs 75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 76 (newHeader, 77 newDecoder, 78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, |
79 self.memFlags, instFlags, base, 80 wbDecl, pcDecl) |
81 82 header_output += newHeader 83 decoder_output += newDecoder 84 exec_output += newExec 85 86 class RfeInst(LoadInst): 87 decConstBase = 'Rfe' 88 --- 11 unchanged lines hidden (view full) --- 100 offset -= 8 101 self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset 102 103 wbDiff = -8 104 if self.add: 105 wbDiff = 8 106 accCode = ''' 107 CPSR cpsr = Cpsr; |
108 URc = cpsr | CondCodes; 109 URa = cSwap<uint32_t>(Mem.ud, cpsr.e); 110 URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); |
111 ''' 112 self.codeBlobs["memacc_code"] = accCode 113 114 wbDecl = None |
115 pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);" 116 |
117 if self.writeback: 118 wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff |
119 self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"], pcDecl) |
120 121 class LoadImmInst(LoadInst): 122 def __init__(self, *args, **kargs): 123 super(LoadImmInst, self).__init__(*args, **kargs) 124 self.offset = self.op + " imm" 125 126 if self.add: 127 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" --- 234 unchanged lines hidden --- |