1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 53 unchanged lines hidden (view full) --- 62 if self.add: 63 self.op = " +" 64 else: 65 self.op = " -" 66 67 self.memFlags = ["ArmISA::TLB::MustBeOne"] 68 self.codeBlobs = {"postacc_code" : ""} 69 |
70 def emitHelper(self, base = 'Memory', wbDecl = None): |
71 72 global header_output, decoder_output, exec_output 73 74 codeBlobs = self.codeBlobs 75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 76 (newHeader, 77 newDecoder, 78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, |
79 self.memFlags, [], base, wbDecl) |
80 81 header_output += newHeader 82 decoder_output += newDecoder 83 exec_output += newExec 84 85 class RfeInst(LoadInst): 86 decConstBase = 'Rfe' 87 --- 20 unchanged lines hidden (view full) --- 108 NPC = cSwap<uint32_t>(Mem.ud, cpsr.e); 109 uint32_t newCpsr = 110 cpsrWriteByInstr(cpsr | CondCodes, 111 cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), 112 0xF, true, sctlr.nmfi); 113 Cpsr = ~CondCodesMask & newCpsr; 114 CondCodes = CondCodesMask & newCpsr; 115 ''' |
116 self.codeBlobs["memacc_code"] = accCode 117 |
118 wbDecl = None 119 if self.writeback: 120 wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff 121 self.emitHelper('RfeOp', wbDecl) |
122 123 class LoadImmInst(LoadInst): 124 def __init__(self, *args, **kargs): 125 super(LoadImmInst, self).__init__(*args, **kargs) 126 self.offset = self.op + " imm" 127 |
128 if self.add: 129 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" 130 else: 131 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);" 132 |
133 class LoadRegInst(LoadInst): 134 def __init__(self, *args, **kargs): 135 super(LoadRegInst, self).__init__(*args, **kargs) 136 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 137 " shiftType, CondCodes<29:>)" |
138 if self.add: 139 self.wbDecl = ''' 140 MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 141 ''' 142 else: 143 self.wbDecl = ''' 144 MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 145 ''' |
146 147 class LoadSingle(LoadInst): 148 def __init__(self, *args, **kargs): 149 super(LoadSingle, self).__init__(*args, **kargs) 150 151 # Build the default class name 152 self.Name = self.nameFunc(self.post, self.add, self.writeback, 153 self.size, self.sign, self.user) --- 30 unchanged lines hidden (view full) --- 184 if self.flavor == "prefetch": 185 accCode = 'uint64_t temp = Mem%s; temp = temp;' 186 elif self.flavor == "fp": 187 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" 188 else: 189 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" 190 accCode = accCode % buildMemSuffix(self.sign, self.size) 191 |
192 self.codeBlobs["memacc_code"] = accCode 193 194 # Push it out to the output files 195 base = buildMemBase(self.basePrefix, self.post, self.writeback) |
196 wbDecl = None 197 if self.writeback: 198 wbDecl = self.wbDecl 199 self.emitHelper(base, wbDecl) |
200 201 def loadImmClassName(post, add, writeback, size=4, sign=False, user=False): 202 return memClassName("LOAD_IMM", post, add, writeback, size, sign, user) 203 204 class LoadImm(LoadImmInst, LoadSingle): |
205 decConstBase = 'LoadImm' |
206 basePrefix = 'MemoryImm' 207 nameFunc = staticmethod(loadImmClassName) 208 209 def loadRegClassName(post, add, writeback, size=4, sign=False, user=False): 210 return memClassName("LOAD_REG", post, add, writeback, size, sign, user) 211 212 class LoadReg(LoadRegInst, LoadSingle): |
213 decConstBase = 'LoadReg' |
214 basePrefix = 'MemoryReg' 215 nameFunc = staticmethod(loadRegClassName) 216 217 class LoadDouble(LoadInst): 218 def __init__(self, *args, **kargs): 219 super(LoadDouble, self).__init__(*args, **kargs) 220 221 # Build the default class name --- 31 unchanged lines hidden (view full) --- 253 ''' 254 else: 255 accCode = ''' 256 uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); 257 FpDest.uw = (uint32_t)swappedMem; 258 FpDest2.uw = (uint32_t)(swappedMem >> 32); 259 ''' 260 |
261 self.codeBlobs["memacc_code"] = accCode 262 263 # Push it out to the output files 264 base = buildMemBase(self.basePrefix, self.post, self.writeback) |
265 wbDecl = None 266 if self.writeback: 267 wbDecl = self.wbDecl 268 self.emitHelper(base, wbDecl) |
269 270 def loadDoubleImmClassName(post, add, writeback): 271 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 272 273 class LoadDoubleImm(LoadImmInst, LoadDouble): 274 decConstBase = 'LoadStoreDImm' 275 basePrefix = 'MemoryDImm' 276 nameFunc = staticmethod(loadDoubleImmClassName) 277 278 def loadDoubleRegClassName(post, add, writeback): 279 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 280 281 class LoadDoubleReg(LoadRegInst, LoadDouble): |
282 decConstBase = 'LoadDReg' |
283 basePrefix = 'MemoryDReg' 284 nameFunc = staticmethod(loadDoubleRegClassName) 285 286 def buildLoads(mnem, size=4, sign=False, user=False): 287 LoadImm(mnem, True, True, True, size, sign, user).emit() 288 LoadReg(mnem, True, True, True, size, sign, user).emit() 289 LoadImm(mnem, True, False, True, size, sign, user).emit() 290 LoadReg(mnem, True, False, True, size, sign, user).emit() --- 68 unchanged lines hidden --- |