1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 79 unchanged lines hidden (view full) --- 88 89 offset = op + " imm" 90 eaCode = "EA = Base" 91 if not post: 92 eaCode += offset 93 eaCode += ";" 94 95 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] |
96 if user: 97 memFlags.append("ArmISA::TLB::UserMode") 98 |
99 if prefetch: 100 Name = "%s_%s" % (mnem.upper(), Name) 101 memFlags.append("Request::PREFETCH") 102 accCode = ''' 103 uint64_t temp = Mem%s;\n 104 temp = temp; 105 ''' % buildMemSuffix(sign, size) 106 elif vldr: --- 70 unchanged lines hidden (view full) --- 177 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 178 " shiftType, CondCodes<29:>)" 179 eaCode = "EA = Base" 180 if not post: 181 eaCode += offset 182 eaCode += ";" 183 184 memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"] |
185 if user: 186 memFlags.append("ArmISA::TLB::UserMode") 187 |
188 if prefetch: 189 Name = "%s_%s" % (mnem.upper(), Name) 190 memFlags.append("Request::PREFETCH") 191 accCode = ''' 192 uint64_t temp = Mem%s;\n 193 temp = temp; 194 ''' % buildMemSuffix(sign, size) 195 else: --- 159 unchanged lines hidden --- |