1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 45 unchanged lines hidden (view full) --- 54 size, sign, user) 55 56 def loadDoubleImmClassName(post, add, writeback): 57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 58 59 def loadDoubleRegClassName(post, add, writeback): 60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 61 |
62 def emitLoad(name, Name, imm, eaCode, accCode, \ 63 memFlags, instFlags, base, double=False): |
64 global header_output, decoder_output, exec_output 65 66 (newHeader, 67 newDecoder, 68 newExec) = loadStoreBase(name, Name, imm, 69 eaCode, accCode, |
70 memFlags, instFlags, double, |
71 base, execTemplateBase = 'Load') 72 73 header_output += newHeader 74 decoder_output += newDecoder 75 exec_output += newExec 76 77 def buildImmLoad(mnem, post, add, writeback, \ 78 size=4, sign=False, user=False, \ --- 60 unchanged lines hidden (view full) --- 139 ''' % buildMemSuffix(sign, size) 140 else: 141 memFlags = [] 142 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size) 143 if writeback: 144 accCode += "Base = Base %s;\n" % offset 145 base = buildMemBase("MemoryReg", post, writeback) 146 |
147 emitLoad(name, Name, False, eaCode, accCode, \ 148 memFlags, [], base) |
149 150 def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False): 151 name = mnem 152 Name = loadDoubleImmClassName(post, add, writeback) 153 154 if add: 155 op = " +" 156 else: 157 op = " -" 158 159 offset = op + " imm" 160 eaCode = "EA = Base" 161 if not post: 162 eaCode += offset 163 eaCode += ";" 164 165 accCode = ''' |
166 Dest = bits(Mem.ud, 31, 0); 167 Dest2 = bits(Mem.ud, 63, 32); |
168 ''' 169 if ldrex: 170 memFlags = ["Request::LLSC"] 171 Name = "%s_%s" % (mnem.upper(), Name) 172 else: 173 memFlags = [] 174 if writeback: 175 accCode += "Base = Base %s;\n" % offset |
176 base = buildMemBase("MemoryDImm", post, writeback) |
177 |
178 emitLoad(name, Name, True, eaCode, accCode, \ 179 memFlags, [], base, double=True) |
180 181 def buildDoubleRegLoad(mnem, post, add, writeback): 182 name = mnem 183 Name = loadDoubleRegClassName(post, add, writeback) 184 185 if add: 186 op = " +" 187 else: 188 op = " -" 189 190 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 191 " shiftType, CondCodes<29:>)" 192 eaCode = "EA = Base" 193 if not post: 194 eaCode += offset 195 eaCode += ";" 196 197 accCode = ''' |
198 Dest = bits(Mem.ud, 31, 0); 199 Dest2 = bits(Mem.ud, 63, 32); |
200 ''' 201 if writeback: 202 accCode += "Base = Base %s;\n" % offset |
203 base = buildMemBase("MemoryDReg", post, writeback) |
204 |
205 emitLoad(name, Name, False, eaCode, accCode, 206 [], [], base, double=True) |
207 208 def buildLoads(mnem, size=4, sign=False, user=False): 209 buildImmLoad(mnem, True, True, True, size, sign, user) 210 buildRegLoad(mnem, True, True, True, size, sign, user) 211 buildImmLoad(mnem, True, False, True, size, sign, user) 212 buildRegLoad(mnem, True, False, True, size, sign, user) 213 buildImmLoad(mnem, False, True, True, size, sign, user) 214 buildRegLoad(mnem, False, True, True, size, sign, user) --- 49 unchanged lines hidden --- |