70c70
< def emitHelper(self, base = 'Memory'):
---
> def emitHelper(self, base = 'Memory', wbDecl = None):
79c79
< self.memFlags, [], base)
---
> self.memFlags, [], base, wbDecl)
116,117d115
< if self.writeback:
< accCode += "Base = Base + %s;\n" % wbDiff
120c118,121
< self.emitHelper('RfeOp')
---
> wbDecl = None
> if self.writeback:
> wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
> self.emitHelper('RfeOp', wbDecl)
126a128,132
> if self.add:
> self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
> else:
> self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
>
131a138,145
> if self.add:
> self.wbDecl = '''
> MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
> '''
> else:
> self.wbDecl = '''
> MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
> '''
178,180d191
< if self.writeback:
< accCode += "Base = Base %s;\n" % self.offset
<
185c196,199
< self.emitHelper(base)
---
> wbDecl = None
> if self.writeback:
> wbDecl = self.wbDecl
> self.emitHelper(base, wbDecl)
191c205
< decConstBase = 'LoadStoreImm'
---
> decConstBase = 'LoadImm'
199c213
< decConstBase = 'LoadStoreReg'
---
> decConstBase = 'LoadReg'
247,249d260
< if self.writeback:
< accCode += "Base = Base %s;\n" % self.offset
<
254c265,268
< self.emitHelper(base)
---
> wbDecl = None
> if self.writeback:
> wbDecl = self.wbDecl
> self.emitHelper(base, wbDecl)
268c282
< decConstBase = 'LoadStoreDReg'
---
> decConstBase = 'LoadDReg'