94a95
> memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
97c98
< memFlags = ["Request::PREFETCH"]
---
> memFlags.append("Request::PREFETCH")
104c105
< memFlags = ["Request::LLSC"]
---
> memFlags.append("Request::LLSC")
106,107d106
< else:
< memFlags = []
108a108,111
>
> if not prefetch and not ldrex:
> memFlags.append("ArmISA::TLB::AllowUnaligned")
>
145c148,149
< newExec) = RfeBase(name, Name, eaCode, accCode, [], [])
---
> newExec) = RfeBase(name, Name, eaCode, accCode,
> ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [])
168a173
> memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"]
171c176
< memFlags = ["Request::PREFETCH"]
---
> memFlags.append("Request::PREFETCH")
177d181
< memFlags = []
180a185,188
>
> if not prefetch:
> memFlags.append("ArmISA::TLB::AllowUnaligned")
>
213a222,224
> memFlags.extend(["ArmISA::TLB::MustBeOne",
> "ArmISA::TLB::AlignWord"])
>
242c253,254
< [], [], base, double=True)
---
> ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"],
> [], base, double=True)