55a56,61
> def loadDoubleImmClassName(post, add, writeback):
> return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
>
> def loadDoubleRegClassName(post, add, writeback):
> return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
>
118a125,175
> def buildDoubleImmLoad(mnem, post, add, writeback):
> name = mnem
> Name = loadDoubleImmClassName(post, add, writeback)
>
> if add:
> op = " +"
> else:
> op = " -"
>
> offset = op + " imm"
> eaCode = "EA = Base"
> if not post:
> eaCode += offset
> eaCode += ";"
>
> accCode = '''
> Rdo = bits(Mem.ud, 31, 0);
> Rde = bits(Mem.ud, 63, 32);
> '''
> if writeback:
> accCode += "Base = Base %s;\n" % offset
> base = buildMemBase("MemoryNewImm", post, writeback)
>
> emitLoad(name, Name, True, eaCode, accCode, [], [], base)
>
> def buildDoubleRegLoad(mnem, post, add, writeback):
> name = mnem
> Name = loadDoubleRegClassName(post, add, writeback)
>
> if add:
> op = " +"
> else:
> op = " -"
>
> offset = op + " shift_rm_imm(Index, shiftAmt," + \
> " shiftType, CondCodes<29:>)"
> eaCode = "EA = Base"
> if not post:
> eaCode += offset
> eaCode += ";"
>
> accCode = '''
> Rdo = bits(Mem.ud, 31, 0);
> Rde = bits(Mem.ud, 63, 32);
> '''
> if writeback:
> accCode += "Base = Base %s;\n" % offset
> base = buildMemBase("MemoryNewReg", post, writeback)
>
> emitLoad(name, Name, False, eaCode, accCode, [], [], base)
>
132a190,203
> def buildDoubleLoads(mnem):
> buildDoubleImmLoad(mnem, True, True, True)
> buildDoubleRegLoad(mnem, True, True, True)
> buildDoubleImmLoad(mnem, True, False, True)
> buildDoubleRegLoad(mnem, True, False, True)
> buildDoubleImmLoad(mnem, False, True, True)
> buildDoubleRegLoad(mnem, False, True, True)
> buildDoubleImmLoad(mnem, False, False, True)
> buildDoubleRegLoad(mnem, False, False, True)
> buildDoubleImmLoad(mnem, False, True, False)
> buildDoubleRegLoad(mnem, False, True, False)
> buildDoubleImmLoad(mnem, False, False, False)
> buildDoubleRegLoad(mnem, False, False, False)
>
142a214,215
>
> buildDoubleLoads("ldrd")