ldr.isa (10869:43b5dd939a49) | ldr.isa (13589:13522f2a5126) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010-2011 ARM Limited | 3// Copyright (c) 2010-2011,2019 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 156 unchanged lines hidden (view full) --- 168 169 self.instFlags = [] 170 if self.flavor == "dprefetch": 171 self.memFlags.append("Request::PREFETCH") 172 self.instFlags = ['IsDataPrefetch'] 173 elif self.flavor == "iprefetch": 174 self.memFlags.append("Request::PREFETCH") 175 self.instFlags = ['IsInstPrefetch'] | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 156 unchanged lines hidden (view full) --- 168 169 self.instFlags = [] 170 if self.flavor == "dprefetch": 171 self.memFlags.append("Request::PREFETCH") 172 self.instFlags = ['IsDataPrefetch'] 173 elif self.flavor == "iprefetch": 174 self.memFlags.append("Request::PREFETCH") 175 self.instFlags = ['IsInstPrefetch'] |
176 elif self.flavor == "exclusive": 177 self.memFlags.append("Request::LLSC") | |
178 elif self.flavor == "normal": 179 self.memFlags.append("ArmISA::TLB::AllowUnaligned") 180 | 176 elif self.flavor == "normal": 177 self.memFlags.append("ArmISA::TLB::AllowUnaligned") 178 |
179 if self.flavor in ("exclusive", "acex"): 180 self.memFlags.append("Request::LLSC") 181 182 if self.flavor in ("acquire", "acex"): 183 self.instFlags.extend(["IsMemBarrier", 184 "IsWriteBarrier", 185 "IsReadBarrier"]) 186 |
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181 # Disambiguate the class name for different flavors of loads 182 if self.flavor != "normal": 183 self.Name = "%s_%s" % (self.name.upper(), self.Name) 184 185 def emit(self): 186 # Address compuation code 187 eaCode = "EA = Base" 188 if not self.post: --- 41 unchanged lines hidden (view full) --- 230 231 class LoadDouble(LoadInst): 232 def __init__(self, *args, **kargs): 233 super(LoadDouble, self).__init__(*args, **kargs) 234 235 # Build the default class name 236 self.Name = self.nameFunc(self.post, self.add, self.writeback) 237 | 187 # Disambiguate the class name for different flavors of loads 188 if self.flavor != "normal": 189 self.Name = "%s_%s" % (self.name.upper(), self.Name) 190 191 def emit(self): 192 # Address compuation code 193 eaCode = "EA = Base" 194 if not self.post: --- 41 unchanged lines hidden (view full) --- 236 237 class LoadDouble(LoadInst): 238 def __init__(self, *args, **kargs): 239 super(LoadDouble, self).__init__(*args, **kargs) 240 241 # Build the default class name 242 self.Name = self.nameFunc(self.post, self.add, self.writeback) 243 |
244 self.instFlags = [] |
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238 # Add memory request flags where necessary | 245 # Add memory request flags where necessary |
239 if self.flavor == "exclusive": | 246 if self.flavor in ("exclusive", "acex"): |
240 self.memFlags.append("Request::LLSC") 241 self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 242 else: 243 self.memFlags.append("ArmISA::TLB::AlignWord") 244 245 # Disambiguate the class name for different flavors of loads 246 if self.flavor != "normal": 247 self.Name = "%s_%s" % (self.name.upper(), self.Name) 248 | 247 self.memFlags.append("Request::LLSC") 248 self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 249 else: 250 self.memFlags.append("ArmISA::TLB::AlignWord") 251 252 # Disambiguate the class name for different flavors of loads 253 if self.flavor != "normal": 254 self.Name = "%s_%s" % (self.name.upper(), self.Name) 255 |
256 if self.flavor in ("acquire", "acex"): 257 self.instFlags.extend(["IsMemBarrier", 258 "IsWriteBarrier", 259 "IsReadBarrier"]) 260 |
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249 def emit(self): 250 # Address computation code 251 eaCode = "EA = Base" 252 if not self.post: 253 eaCode += self.offset 254 eaCode += ";" 255 256 if self.flavor == "fp": --- 17 unchanged lines hidden (view full) --- 274 275 self.codeBlobs["memacc_code"] = accCode 276 277 # Push it out to the output files 278 base = buildMemBase(self.basePrefix, self.post, self.writeback) 279 wbDecl = None 280 if self.writeback: 281 wbDecl = self.wbDecl | 261 def emit(self): 262 # Address computation code 263 eaCode = "EA = Base" 264 if not self.post: 265 eaCode += self.offset 266 eaCode += ";" 267 268 if self.flavor == "fp": --- 17 unchanged lines hidden (view full) --- 286 287 self.codeBlobs["memacc_code"] = accCode 288 289 # Push it out to the output files 290 base = buildMemBase(self.basePrefix, self.post, self.writeback) 291 wbDecl = None 292 if self.writeback: 293 wbDecl = self.wbDecl |
282 self.emitHelper(base, wbDecl) | 294 self.emitHelper(base, wbDecl, self.instFlags) |
283 284 def loadDoubleImmClassName(post, add, writeback): 285 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 286 287 class LoadDoubleImm(LoadImmInst, LoadDouble): 288 decConstBase = 'LoadStoreDImm' 289 basePrefix = 'MemoryDImm' 290 nameFunc = staticmethod(loadDoubleImmClassName) --- 69 unchanged lines hidden (view full) --- 360 buildPrefetches("pldw", "dprefetch") 361 buildPrefetches("pli", "iprefetch") 362 363 LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit() 364 LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit() 365 LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit() 366 LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit() 367 | 295 296 def loadDoubleImmClassName(post, add, writeback): 297 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 298 299 class LoadDoubleImm(LoadImmInst, LoadDouble): 300 decConstBase = 'LoadStoreDImm' 301 basePrefix = 'MemoryDImm' 302 nameFunc = staticmethod(loadDoubleImmClassName) --- 69 unchanged lines hidden (view full) --- 372 buildPrefetches("pldw", "dprefetch") 373 buildPrefetches("pli", "iprefetch") 374 375 LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit() 376 LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit() 377 LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit() 378 LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit() 379 |
380 LoadImm("lda", False, True, False, size=4, flavor="acquire").emit() 381 LoadImm("ldah", False, True, False, size=2, flavor="acquire").emit() 382 LoadImm("ldab", False, True, False, size=1, flavor="acquire").emit() 383 LoadImm("ldaex", False, True, False, size=4, flavor="acex").emit() 384 LoadImm("ldaexh", False, True, False, size=2, flavor="acex").emit() 385 LoadImm("ldaexb", False, True, False, size=1, flavor="acex").emit() 386 LoadDoubleImm("ldaexd", False, True, False, flavor="acex").emit() 387 |
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368 LoadImm("vldr", False, True, False, size=4, flavor="fp").emit() 369 LoadImm("vldr", False, False, False, size=4, flavor="fp").emit() 370 LoadDoubleImm("vldr", False, True, False, flavor="fp").emit() 371 LoadDoubleImm("vldr", False, False, False, flavor="fp").emit() 372}}; | 388 LoadImm("vldr", False, True, False, size=4, flavor="fp").emit() 389 LoadImm("vldr", False, False, False, size=4, flavor="fp").emit() 390 LoadDoubleImm("vldr", False, True, False, flavor="fp").emit() 391 LoadDoubleImm("vldr", False, False, False, flavor="fp").emit() 392}}; |