1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 def loadImmClassName(post, add, writeback, \
47 size=4, sign=False, user=False):
48 return memClassName("LOAD_IMM", post, add, writeback,
49 size, sign, user)
50
51 def loadRegClassName(post, add, writeback, \
52 size=4, sign=False, user=False):
53 return memClassName("LOAD_REG", post, add, writeback,
54 size, sign, user)
55
56 def loadDoubleImmClassName(post, add, writeback):
57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
58
59 def loadDoubleRegClassName(post, add, writeback):
60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
62 def emitLoad(name, Name, imm, eaCode, accCode, \
63 memFlags, instFlags, base, double=False):
64 global header_output, decoder_output, exec_output
65
66 (newHeader,
67 newDecoder,
68 newExec) = loadStoreBase(name, Name, imm,
69 eaCode, accCode,
70 memFlags, instFlags, double,
71 base, execTemplateBase = 'Load')
72
73 header_output += newHeader
74 decoder_output += newDecoder
75 exec_output += newExec
76
77 def buildImmLoad(mnem, post, add, writeback, \
78 size=4, sign=False, user=False, \
79 prefetch=False, ldrex=False):
80 name = mnem
81 Name = loadImmClassName(post, add, writeback, \
82 size, sign, user)
83
84 if add:
85 op = " +"
86 else:
87 op = " -"
88
89 offset = op + " imm"
90 eaCode = "EA = Base"
91 if not post:
92 eaCode += offset
93 eaCode += ";"
94
95 if prefetch:
96 Name = "%s_%s" % (mnem.upper(), Name)
97 memFlags = ["Request::PREFETCH"]
98 accCode = '''
99 uint64_t temp = Mem%s;\n
100 temp = temp;
101 ''' % buildMemSuffix(sign, size)
102 else:
103 if ldrex:
104 memFlags = ["Request::LLSC"]
105 Name = "%s_%s" % (mnem.upper(), Name)
106 else:
107 memFlags = []
108 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
109 if writeback:
110 accCode += "Base = Base %s;\n" % offset
111 base = buildMemBase("MemoryImm", post, writeback)
112
113 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
114
115 def buildRfeLoad(mnem, post, add, writeback):
116 name = mnem
117 Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
118
119 offset = 0
120 if post != add:
121 offset += 4
122 if not add:
123 offset -= 8
124
125 eaCode = "EA = Base + %d;" % offset
126
127 wbDiff = -8
128 if add:
129 wbDiff = 8
130 accCode = '''
131 NPC = bits(Mem.ud, 31, 0);
132 uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes,
133 bits(Mem.ud, 63, 32),
134 0xF, true);
135 Cpsr = ~CondCodesMask & newCpsr;
136 CondCodes = CondCodesMask & newCpsr;
137 '''
138 if writeback:
139 accCode += "Base = Base + %s;\n" % wbDiff
140
141 global header_output, decoder_output, exec_output
142
143 (newHeader,
144 newDecoder,
145 newExec) = RfeBase(name, Name, eaCode, accCode, [], [])
146
147 header_output += newHeader
148 decoder_output += newDecoder
149 exec_output += newExec
150
151 def buildRegLoad(mnem, post, add, writeback, \
152 size=4, sign=False, user=False, prefetch=False):
153 name = mnem
154 Name = loadRegClassName(post, add, writeback,
155 size, sign, user)
156
157 if add:
158 op = " +"
159 else:
160 op = " -"
161
162 offset = op + " shift_rm_imm(Index, shiftAmt," + \
163 " shiftType, CondCodes<29:>)"
164 eaCode = "EA = Base"
165 if not post:
166 eaCode += offset
167 eaCode += ";"
168
169 if prefetch:
170 Name = "%s_%s" % (mnem.upper(), Name)
171 memFlags = ["Request::PREFETCH"]
172 accCode = '''
173 uint64_t temp = Mem%s;\n
174 temp = temp;
175 ''' % buildMemSuffix(sign, size)
176 else:
177 memFlags = []
178 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
179 if writeback:
180 accCode += "Base = Base %s;\n" % offset
181 base = buildMemBase("MemoryReg", post, writeback)
182
183 emitLoad(name, Name, False, eaCode, accCode, \
184 memFlags, [], base)
185
186 def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False):
187 name = mnem
188 Name = loadDoubleImmClassName(post, add, writeback)
189
190 if add:
191 op = " +"
192 else:
193 op = " -"
194
195 offset = op + " imm"
196 eaCode = "EA = Base"
197 if not post:
198 eaCode += offset
199 eaCode += ";"
200
201 accCode = '''
202 Dest = bits(Mem.ud, 31, 0);
203 Dest2 = bits(Mem.ud, 63, 32);
204 '''
205 if ldrex:
206 memFlags = ["Request::LLSC"]
207 Name = "%s_%s" % (mnem.upper(), Name)
208 else:
209 memFlags = []
210 if writeback:
211 accCode += "Base = Base %s;\n" % offset
212 base = buildMemBase("MemoryDImm", post, writeback)
213
214 emitLoad(name, Name, True, eaCode, accCode, \
215 memFlags, [], base, double=True)
216
217 def buildDoubleRegLoad(mnem, post, add, writeback):
218 name = mnem
219 Name = loadDoubleRegClassName(post, add, writeback)
220
221 if add:
222 op = " +"
223 else:
224 op = " -"
225
226 offset = op + " shift_rm_imm(Index, shiftAmt," + \
227 " shiftType, CondCodes<29:>)"
228 eaCode = "EA = Base"
229 if not post:
230 eaCode += offset
231 eaCode += ";"
232
233 accCode = '''
234 Dest = bits(Mem.ud, 31, 0);
235 Dest2 = bits(Mem.ud, 63, 32);
236 '''
237 if writeback:
238 accCode += "Base = Base %s;\n" % offset
239 base = buildMemBase("MemoryDReg", post, writeback)
240
241 emitLoad(name, Name, False, eaCode, accCode,
242 [], [], base, double=True)
243
244 def buildLoads(mnem, size=4, sign=False, user=False):
245 buildImmLoad(mnem, True, True, True, size, sign, user)
246 buildRegLoad(mnem, True, True, True, size, sign, user)
247 buildImmLoad(mnem, True, False, True, size, sign, user)
248 buildRegLoad(mnem, True, False, True, size, sign, user)
249 buildImmLoad(mnem, False, True, True, size, sign, user)
250 buildRegLoad(mnem, False, True, True, size, sign, user)
251 buildImmLoad(mnem, False, False, True, size, sign, user)
252 buildRegLoad(mnem, False, False, True, size, sign, user)
253 buildImmLoad(mnem, False, True, False, size, sign, user)
254 buildRegLoad(mnem, False, True, False, size, sign, user)
255 buildImmLoad(mnem, False, False, False, size, sign, user)
256 buildRegLoad(mnem, False, False, False, size, sign, user)
257
258 def buildDoubleLoads(mnem):
259 buildDoubleImmLoad(mnem, True, True, True)
260 buildDoubleRegLoad(mnem, True, True, True)
261 buildDoubleImmLoad(mnem, True, False, True)
262 buildDoubleRegLoad(mnem, True, False, True)
263 buildDoubleImmLoad(mnem, False, True, True)
264 buildDoubleRegLoad(mnem, False, True, True)
265 buildDoubleImmLoad(mnem, False, False, True)
266 buildDoubleRegLoad(mnem, False, False, True)
267 buildDoubleImmLoad(mnem, False, True, False)
268 buildDoubleRegLoad(mnem, False, True, False)
269 buildDoubleImmLoad(mnem, False, False, False)
270 buildDoubleRegLoad(mnem, False, False, False)
271
272 def buildRfeLoads(mnem):
273 buildRfeLoad(mnem, True, True, True)
274 buildRfeLoad(mnem, True, True, False)
275 buildRfeLoad(mnem, True, False, True)
276 buildRfeLoad(mnem, True, False, False)
277 buildRfeLoad(mnem, False, True, True)
278 buildRfeLoad(mnem, False, True, False)
279 buildRfeLoad(mnem, False, False, True)
280 buildRfeLoad(mnem, False, False, False)
281
282 def buildPrefetches(mnem):
283 buildRegLoad(mnem, False, False, False, size=1, prefetch=True)
284 buildImmLoad(mnem, False, False, False, size=1, prefetch=True)
285 buildRegLoad(mnem, False, True, False, size=1, prefetch=True)
286 buildImmLoad(mnem, False, True, False, size=1, prefetch=True)
287
288 buildLoads("ldr")
289 buildLoads("ldrt", user=True)
290 buildLoads("ldrb", size=1)
291 buildLoads("ldrbt", size=1, user=True)
292 buildLoads("ldrsb", size=1, sign=True)
293 buildLoads("ldrsbt", size=1, sign=True, user=True)
294 buildLoads("ldrh", size=2)
295 buildLoads("ldrht", size=2, user=True)
296 buildLoads("hdrsh", size=2, sign=True)
297 buildLoads("ldrsht", size=2, sign=True, user=True)
298
299 buildDoubleLoads("ldrd")
300
301 buildRfeLoads("rfe")
302
303 buildPrefetches("pld")
304 buildPrefetches("pldw")
305 buildPrefetches("pli")
306
307 buildImmLoad("ldrex", False, True, False, size=4, ldrex=True)
308 buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True)
309 buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True)
310 buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True)
311}};