1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 def loadImmClassName(post, add, writeback, \
47 size=4, sign=False, user=False):
48 return memClassName("LOAD_IMM", post, add, writeback,
49 size, sign, user)
50
51 def loadRegClassName(post, add, writeback, \
52 size=4, sign=False, user=False):
53 return memClassName("LOAD_REG", post, add, writeback,
54 size, sign, user)
55
56 def loadDoubleImmClassName(post, add, writeback):
57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
58
59 def loadDoubleRegClassName(post, add, writeback):
60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
62 def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
63 global header_output, decoder_output, exec_output
64
65 (newHeader,
66 newDecoder,
67 newExec) = loadStoreBase(name, Name, imm,
68 eaCode, accCode,
69 memFlags, instFlags,
70 base, execTemplateBase = 'Load')
71
72 header_output += newHeader
73 decoder_output += newDecoder
74 exec_output += newExec
75
76 def buildImmLoad(mnem, post, add, writeback, \
77 size=4, sign=False, user=False):
78 name = mnem
79 Name = loadImmClassName(post, add, writeback, \
80 size, sign, user)
81
82 if add:
83 op = " +"
84 else:
85 op = " -"
86
87 offset = op + " imm"
88 eaCode = "EA = Base"
89 if not post:
90 eaCode += offset
91 eaCode += ";"
92
93 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
94 if writeback:
95 accCode += "Base = Base %s;\n" % offset
96 base = buildMemBase("MemoryImm", post, writeback)
97
98 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
99
100 def buildRegLoad(mnem, post, add, writeback, \
101 size=4, sign=False, user=False):
102 name = mnem
103 Name = loadRegClassName(post, add, writeback,
104 size, sign, user)
105
106 if add:
107 op = " +"
108 else:
109 op = " -"
110
111 offset = op + " shift_rm_imm(Index, shiftAmt," + \
112 " shiftType, CondCodes<29:>)"
113 eaCode = "EA = Base"
114 if not post:
115 eaCode += offset
116 eaCode += ";"
117
118 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
119 if writeback:
120 accCode += "Base = Base %s;\n" % offset
121 base = buildMemBase("MemoryReg", post, writeback)
122
123 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
124
125 def buildDoubleImmLoad(mnem, post, add, writeback):
126 name = mnem
127 Name = loadDoubleImmClassName(post, add, writeback)
128
129 if add:
130 op = " +"
131 else:
132 op = " -"
133
134 offset = op + " imm"
135 eaCode = "EA = Base"
136 if not post:
137 eaCode += offset
138 eaCode += ";"
139
140 accCode = '''
141 Rdo = bits(Mem.ud, 31, 0);
142 Rde = bits(Mem.ud, 63, 32);
143 '''
144 if writeback:
145 accCode += "Base = Base %s;\n" % offset
146 base = buildMemBase("MemoryImm", post, writeback)
147
148 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
149
150 def buildDoubleRegLoad(mnem, post, add, writeback):
151 name = mnem
152 Name = loadDoubleRegClassName(post, add, writeback)
153
154 if add:
155 op = " +"
156 else:
157 op = " -"
158
159 offset = op + " shift_rm_imm(Index, shiftAmt," + \
160 " shiftType, CondCodes<29:>)"
161 eaCode = "EA = Base"
162 if not post:
163 eaCode += offset
164 eaCode += ";"
165
166 accCode = '''
167 Rdo = bits(Mem.ud, 31, 0);
168 Rde = bits(Mem.ud, 63, 32);
169 '''
170 if writeback:
171 accCode += "Base = Base %s;\n" % offset
172 base = buildMemBase("MemoryReg", post, writeback)
173
174 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
175
176 def buildLoads(mnem, size=4, sign=False, user=False):
177 buildImmLoad(mnem, True, True, True, size, sign, user)
178 buildRegLoad(mnem, True, True, True, size, sign, user)
179 buildImmLoad(mnem, True, False, True, size, sign, user)
180 buildRegLoad(mnem, True, False, True, size, sign, user)
181 buildImmLoad(mnem, False, True, True, size, sign, user)
182 buildRegLoad(mnem, False, True, True, size, sign, user)
183 buildImmLoad(mnem, False, False, True, size, sign, user)
184 buildRegLoad(mnem, False, False, True, size, sign, user)
185 buildImmLoad(mnem, False, True, False, size, sign, user)
186 buildRegLoad(mnem, False, True, False, size, sign, user)
187 buildImmLoad(mnem, False, False, False, size, sign, user)
188 buildRegLoad(mnem, False, False, False, size, sign, user)
189
190 def buildDoubleLoads(mnem):
191 buildDoubleImmLoad(mnem, True, True, True)
192 buildDoubleRegLoad(mnem, True, True, True)
193 buildDoubleImmLoad(mnem, True, False, True)
194 buildDoubleRegLoad(mnem, True, False, True)
195 buildDoubleImmLoad(mnem, False, True, True)
196 buildDoubleRegLoad(mnem, False, True, True)
197 buildDoubleImmLoad(mnem, False, False, True)
198 buildDoubleRegLoad(mnem, False, False, True)
199 buildDoubleImmLoad(mnem, False, True, False)
200 buildDoubleRegLoad(mnem, False, True, False)
201 buildDoubleImmLoad(mnem, False, False, False)
202 buildDoubleRegLoad(mnem, False, False, False)
203
204 buildLoads("ldr")
205 buildLoads("ldrt", user=True)
206 buildLoads("ldrb", size=1)
207 buildLoads("ldrbt", size=1, user=True)
208 buildLoads("ldrsb", size=1, sign=True)
209 buildLoads("ldrsbt", size=1, sign=True, user=True)
210 buildLoads("ldrh", size=2)
211 buildLoads("ldrht", size=2, user=True)
212 buildLoads("hdrsh", size=2, sign=True)
213 buildLoads("ldrsht", size=2, sign=True, user=True)
214
215 buildDoubleLoads("ldrd")
216}};