1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 147 unchanged lines hidden (view full) ---

156 self.Name = self.nameFunc(self.post, self.add, self.writeback,
157 self.size, self.sign, self.user)
158
159 # Add memory request flags where necessary
160 self.memFlags.append("%d" % (self.size - 1))
161 if self.user:
162 self.memFlags.append("ArmISA::TLB::UserMode")
163
164 if self.flavor == "prefetch":
165 self.memFlags.append("Request::PREFETCH")
166 elif self.flavor == "exclusive":
167 self.memFlags.append("Request::LLSC")
168 elif self.flavor == "normal":
169 self.memFlags.append("ArmISA::TLB::AllowUnaligned")
170
171 # Disambiguate the class name for different flavors of loads
172 if self.flavor != "normal":
173 self.Name = "%s_%s" % (self.name.upper(), self.Name)

--- 6 unchanged lines hidden (view full) ---

180 eaCode += ";"
181
182 if self.flavor == "fp":
183 eaCode += vfpEnabledCheckCode
184
185 self.codeBlobs["ea_code"] = eaCode
186
187 # Code that actually handles the access
188 if self.flavor == "prefetch":
189 accCode = 'uint64_t temp = Mem%s; temp = temp;'
190 elif self.flavor == "fp":
191 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
192 else:
193 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
194 accCode = accCode % buildMemSuffix(self.sign, self.size)
195
196 self.codeBlobs["memacc_code"] = accCode
197
198 # Push it out to the output files
199 base = buildMemBase(self.basePrefix, self.post, self.writeback)
200 wbDecl = None
201 if self.writeback:
202 wbDecl = self.wbDecl
203 self.emitHelper(base, wbDecl)
204
205 def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
206 return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
207
208 class LoadImm(LoadImmInst, LoadSingle):
209 decConstBase = 'LoadImm'
210 basePrefix = 'MemoryImm'
211 nameFunc = staticmethod(loadImmClassName)

--- 108 unchanged lines hidden (view full) ---

320 RfeInst(mnem, True, True, False).emit()
321 RfeInst(mnem, True, False, True).emit()
322 RfeInst(mnem, True, False, False).emit()
323 RfeInst(mnem, False, True, True).emit()
324 RfeInst(mnem, False, True, False).emit()
325 RfeInst(mnem, False, False, True).emit()
326 RfeInst(mnem, False, False, False).emit()
327
328 def buildPrefetches(mnem):
329 LoadReg(mnem, False, False, False, size=1, flavor="prefetch").emit()
330 LoadImm(mnem, False, False, False, size=1, flavor="prefetch").emit()
331 LoadReg(mnem, False, True, False, size=1, flavor="prefetch").emit()
332 LoadImm(mnem, False, True, False, size=1, flavor="prefetch").emit()
333
334 buildLoads("ldr")
335 buildLoads("ldrt", user=True)
336 buildLoads("ldrb", size=1)
337 buildLoads("ldrbt", size=1, user=True)
338 buildLoads("ldrsb", size=1, sign=True)
339 buildLoads("ldrsbt", size=1, sign=True, user=True)
340 buildLoads("ldrh", size=2)
341 buildLoads("ldrht", size=2, user=True)
342 buildLoads("hdrsh", size=2, sign=True)
343 buildLoads("ldrsht", size=2, sign=True, user=True)
344
345 buildDoubleLoads("ldrd")
346
347 buildRfeLoads("rfe")
348
349 buildPrefetches("pld")
350 buildPrefetches("pldw")
351 buildPrefetches("pli")
352
353 LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit()
354 LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit()
355 LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit()
356 LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit()
357
358 LoadImm("vldr", False, True, False, size=4, flavor="fp").emit()
359 LoadImm("vldr", False, False, False, size=4, flavor="fp").emit()
360 LoadDoubleImm("vldr", False, True, False, flavor="fp").emit()
361 LoadDoubleImm("vldr", False, False, False, flavor="fp").emit()
362}};