1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = {"postacc_code" : ""}
69
70 def emitHelper(self, base = 'Memory'):
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
79 self.memFlags, [], base)
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class RfeInst(LoadInst):
86 decConstBase = 'Rfe'
87

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108 NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
109 uint32_t newCpsr =
110 cpsrWriteByInstr(cpsr | CondCodes,
111 cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
112 0xF, true, sctlr.nmfi);
113 Cpsr = ~CondCodesMask & newCpsr;
114 CondCodes = CondCodesMask & newCpsr;
115 '''
116 if self.writeback:
117 accCode += "Base = Base + %s;\n" % wbDiff
118 self.codeBlobs["memacc_code"] = accCode
119
120 self.emitHelper('RfeOp')
121
122 class LoadImmInst(LoadInst):
123 def __init__(self, *args, **kargs):
124 super(LoadImmInst, self).__init__(*args, **kargs)
125 self.offset = self.op + " imm"
126
127 class LoadRegInst(LoadInst):
128 def __init__(self, *args, **kargs):
129 super(LoadRegInst, self).__init__(*args, **kargs)
130 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
131 " shiftType, CondCodes<29:>)"
132
133 class LoadSingle(LoadInst):
134 def __init__(self, *args, **kargs):
135 super(LoadSingle, self).__init__(*args, **kargs)
136
137 # Build the default class name
138 self.Name = self.nameFunc(self.post, self.add, self.writeback,
139 self.size, self.sign, self.user)

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170 if self.flavor == "prefetch":
171 accCode = 'uint64_t temp = Mem%s; temp = temp;'
172 elif self.flavor == "fp":
173 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
174 else:
175 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
176 accCode = accCode % buildMemSuffix(self.sign, self.size)
177
178 if self.writeback:
179 accCode += "Base = Base %s;\n" % self.offset
180
181 self.codeBlobs["memacc_code"] = accCode
182
183 # Push it out to the output files
184 base = buildMemBase(self.basePrefix, self.post, self.writeback)
185 self.emitHelper(base)
186
187 def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
188 return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
189
190 class LoadImm(LoadImmInst, LoadSingle):
191 decConstBase = 'LoadStoreImm'
192 basePrefix = 'MemoryImm'
193 nameFunc = staticmethod(loadImmClassName)
194
195 def loadRegClassName(post, add, writeback, size=4, sign=False, user=False):
196 return memClassName("LOAD_REG", post, add, writeback, size, sign, user)
197
198 class LoadReg(LoadRegInst, LoadSingle):
199 decConstBase = 'LoadStoreReg'
200 basePrefix = 'MemoryReg'
201 nameFunc = staticmethod(loadRegClassName)
202
203 class LoadDouble(LoadInst):
204 def __init__(self, *args, **kargs):
205 super(LoadDouble, self).__init__(*args, **kargs)
206
207 # Build the default class name

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239 '''
240 else:
241 accCode = '''
242 uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e);
243 FpDest.uw = (uint32_t)swappedMem;
244 FpDest2.uw = (uint32_t)(swappedMem >> 32);
245 '''
246
247 if self.writeback:
248 accCode += "Base = Base %s;\n" % self.offset
249
250 self.codeBlobs["memacc_code"] = accCode
251
252 # Push it out to the output files
253 base = buildMemBase(self.basePrefix, self.post, self.writeback)
254 self.emitHelper(base)
255
256 def loadDoubleImmClassName(post, add, writeback):
257 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
258
259 class LoadDoubleImm(LoadImmInst, LoadDouble):
260 decConstBase = 'LoadStoreDImm'
261 basePrefix = 'MemoryDImm'
262 nameFunc = staticmethod(loadDoubleImmClassName)
263
264 def loadDoubleRegClassName(post, add, writeback):
265 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
266
267 class LoadDoubleReg(LoadRegInst, LoadDouble):
268 decConstBase = 'LoadStoreDReg'
269 basePrefix = 'MemoryDReg'
270 nameFunc = staticmethod(loadDoubleRegClassName)
271
272 def buildLoads(mnem, size=4, sign=False, user=False):
273 LoadImm(mnem, True, True, True, size, sign, user).emit()
274 LoadReg(mnem, True, True, True, size, sign, user).emit()
275 LoadImm(mnem, True, False, True, size, sign, user).emit()
276 LoadReg(mnem, True, False, True, size, sign, user).emit()

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