1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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87 op = " -"
88
89 offset = op + " imm"
90 eaCode = "EA = Base"
91 if not post:
92 eaCode += offset
93 eaCode += ";"
94
95 if prefetch:
96 Name = "%s_%s" % (mnem.upper(), Name)
97 memFlags = ["Request::PREFETCH"]
98 accCode = '''
99 uint64_t temp = Mem%s;\n
100 temp = temp;
101 ''' % buildMemSuffix(sign, size)
102 else:
103 if ldrex:
104 memFlags = ["Request::LLSC"]
105 Name = "%s_%s" % (mnem.upper(), Name)
106 else:
107 memFlags = []
108 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
109 if writeback:
110 accCode += "Base = Base %s;\n" % offset
111 base = buildMemBase("MemoryImm", post, writeback)
112
113 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
114
115 def buildRfeLoad(mnem, post, add, writeback):
116 name = mnem

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137 '''
138 if writeback:
139 accCode += "Base = Base + %s;\n" % wbDiff
140
141 global header_output, decoder_output, exec_output
142
143 (newHeader,
144 newDecoder,
145 newExec) = RfeBase(name, Name, eaCode, accCode, [], [])
146
147 header_output += newHeader
148 decoder_output += newDecoder
149 exec_output += newExec
150
151 def buildRegLoad(mnem, post, add, writeback, \
152 size=4, sign=False, user=False, prefetch=False):
153 name = mnem

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161
162 offset = op + " shift_rm_imm(Index, shiftAmt," + \
163 " shiftType, CondCodes<29:>)"
164 eaCode = "EA = Base"
165 if not post:
166 eaCode += offset
167 eaCode += ";"
168
169 if prefetch:
170 Name = "%s_%s" % (mnem.upper(), Name)
171 memFlags = ["Request::PREFETCH"]
172 accCode = '''
173 uint64_t temp = Mem%s;\n
174 temp = temp;
175 ''' % buildMemSuffix(sign, size)
176 else:
177 memFlags = []
178 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
179 if writeback:
180 accCode += "Base = Base %s;\n" % offset
181 base = buildMemBase("MemoryReg", post, writeback)
182
183 emitLoad(name, Name, False, eaCode, accCode, \
184 memFlags, [], base)
185
186 def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False):
187 name = mnem
188 Name = loadDoubleImmClassName(post, add, writeback)

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206 memFlags = ["Request::LLSC"]
207 Name = "%s_%s" % (mnem.upper(), Name)
208 else:
209 memFlags = []
210 if writeback:
211 accCode += "Base = Base %s;\n" % offset
212 base = buildMemBase("MemoryDImm", post, writeback)
213
214 emitLoad(name, Name, True, eaCode, accCode, \
215 memFlags, [], base, double=True)
216
217 def buildDoubleRegLoad(mnem, post, add, writeback):
218 name = mnem
219 Name = loadDoubleRegClassName(post, add, writeback)
220
221 if add:

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234 Dest = bits(Mem.ud, 31, 0);
235 Dest2 = bits(Mem.ud, 63, 32);
236 '''
237 if writeback:
238 accCode += "Base = Base %s;\n" % offset
239 base = buildMemBase("MemoryDReg", post, writeback)
240
241 emitLoad(name, Name, False, eaCode, accCode,
242 [], [], base, double=True)
243
244 def buildLoads(mnem, size=4, sign=False, user=False):
245 buildImmLoad(mnem, True, True, True, size, sign, user)
246 buildRegLoad(mnem, True, True, True, size, sign, user)
247 buildImmLoad(mnem, True, False, True, size, sign, user)
248 buildRegLoad(mnem, True, False, True, size, sign, user)
249 buildImmLoad(mnem, False, True, True, size, sign, user)
250 buildRegLoad(mnem, False, True, True, size, sign, user)

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