1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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69 memFlags, instFlags,
70 base, execTemplateBase = 'Load')
71
72 header_output += newHeader
73 decoder_output += newDecoder
74 exec_output += newExec
75
76 def buildImmLoad(mnem, post, add, writeback, \
77 size=4, sign=False, user=False):
78 name = mnem
79 Name = loadImmClassName(post, add, writeback, \
80 size, sign, user)
81
82 if add:
83 op = " +"
84 else:
85 op = " -"
86
87 offset = op + " imm"
88 eaCode = "EA = Base"
89 if not post:
90 eaCode += offset
91 eaCode += ";"
92
93 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
94 if writeback:
95 accCode += "Base = Base %s;\n" % offset
96 base = buildMemBase("MemoryImm", post, writeback)
97
98 emitLoad(name, Name, True, eaCode, accCode, [], [], base)
99
100 def buildRegLoad(mnem, post, add, writeback, \
101 size=4, sign=False, user=False):
102 name = mnem
103 Name = loadRegClassName(post, add, writeback,
104 size, sign, user)
105
106 if add:
107 op = " +"
108 else:
109 op = " -"
110
111 offset = op + " shift_rm_imm(Index, shiftAmt," + \
112 " shiftType, CondCodes<29:>)"
113 eaCode = "EA = Base"
114 if not post:
115 eaCode += offset
116 eaCode += ";"
117
118 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
119 if writeback:
120 accCode += "Base = Base %s;\n" % offset
121 base = buildMemBase("MemoryReg", post, writeback)
122
123 emitLoad(name, Name, False, eaCode, accCode, [], [], base)
124
125 def buildDoubleImmLoad(mnem, post, add, writeback):
126 name = mnem
127 Name = loadDoubleImmClassName(post, add, writeback)
128
129 if add:
130 op = " +"
131 else:

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196 buildDoubleRegLoad(mnem, False, True, True)
197 buildDoubleImmLoad(mnem, False, False, True)
198 buildDoubleRegLoad(mnem, False, False, True)
199 buildDoubleImmLoad(mnem, False, True, False)
200 buildDoubleRegLoad(mnem, False, True, False)
201 buildDoubleImmLoad(mnem, False, False, False)
202 buildDoubleRegLoad(mnem, False, False, False)
203
204 buildLoads("ldr")
205 buildLoads("ldrt", user=True)
206 buildLoads("ldrb", size=1)
207 buildLoads("ldrbt", size=1, user=True)
208 buildLoads("ldrsb", size=1, sign=True)
209 buildLoads("ldrsbt", size=1, sign=True, user=True)
210 buildLoads("ldrh", size=2)
211 buildLoads("ldrht", size=2, user=True)
212 buildLoads("hdrsh", size=2, sign=True)
213 buildLoads("ldrsht", size=2, sign=True, user=True)
214
215 buildDoubleLoads("ldrd")
216}};