1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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168
169 self.instFlags = []
170 if self.flavor == "dprefetch":
171 self.memFlags.append("Request::PREFETCH")
172 self.instFlags = ['IsDataPrefetch']
173 elif self.flavor == "iprefetch":
174 self.memFlags.append("Request::PREFETCH")
175 self.instFlags = ['IsInstPrefetch']
176 elif self.flavor == "exclusive":
177 self.memFlags.append("Request::LLSC")
178 elif self.flavor == "normal":
179 self.memFlags.append("ArmISA::TLB::AllowUnaligned")
180
181 # Disambiguate the class name for different flavors of loads
182 if self.flavor != "normal":
183 self.Name = "%s_%s" % (self.name.upper(), self.Name)
184
185 def emit(self):
186 # Address compuation code
187 eaCode = "EA = Base"
188 if not self.post:

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230
231 class LoadDouble(LoadInst):
232 def __init__(self, *args, **kargs):
233 super(LoadDouble, self).__init__(*args, **kargs)
234
235 # Build the default class name
236 self.Name = self.nameFunc(self.post, self.add, self.writeback)
237
238 # Add memory request flags where necessary
239 if self.flavor == "exclusive":
240 self.memFlags.append("Request::LLSC")
241 self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
242 else:
243 self.memFlags.append("ArmISA::TLB::AlignWord")
244
245 # Disambiguate the class name for different flavors of loads
246 if self.flavor != "normal":
247 self.Name = "%s_%s" % (self.name.upper(), self.Name)
248
249 def emit(self):
250 # Address computation code
251 eaCode = "EA = Base"
252 if not self.post:
253 eaCode += self.offset
254 eaCode += ";"
255
256 if self.flavor == "fp":

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274
275 self.codeBlobs["memacc_code"] = accCode
276
277 # Push it out to the output files
278 base = buildMemBase(self.basePrefix, self.post, self.writeback)
279 wbDecl = None
280 if self.writeback:
281 wbDecl = self.wbDecl
282 self.emitHelper(base, wbDecl)
283
284 def loadDoubleImmClassName(post, add, writeback):
285 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
286
287 class LoadDoubleImm(LoadImmInst, LoadDouble):
288 decConstBase = 'LoadStoreDImm'
289 basePrefix = 'MemoryDImm'
290 nameFunc = staticmethod(loadDoubleImmClassName)

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360 buildPrefetches("pldw", "dprefetch")
361 buildPrefetches("pli", "iprefetch")
362
363 LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit()
364 LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit()
365 LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit()
366 LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit()
367
368 LoadImm("vldr", False, True, False, size=4, flavor="fp").emit()
369 LoadImm("vldr", False, False, False, size=4, flavor="fp").emit()
370 LoadDoubleImm("vldr", False, True, False, flavor="fp").emit()
371 LoadDoubleImm("vldr", False, False, False, flavor="fp").emit()
372}};